1; REQUIRES: asserts
2; RUN: llc -mtriple=riscv32 -debug-only=machine-scheduler < %s \
3; RUN:   -o /dev/null 2>&1 | FileCheck %s
4; RUN: llc -mtriple=riscv64 -debug-only=machine-scheduler < %s \
5; RUN:   -o /dev/null 2>&1 | FileCheck %s
6
7; This test exercises the areMemAccessesTriviallyDisjoint hook.
8; Test that the two stores are disjoint memory accesses. If the corresponding
9; store machine instructions don't depend on each other, the second store should
10; not appear in the successors list of the first one and the first one should
11; not appear on the predecessors list of the second one.
12define i32 @test_disjoint(i32* %P, i32 %v) {
13entry:
14; CHECK: ********** MI Scheduling **********
15; CHECK-LABEL: test_disjoint:%bb.0
16; CHECK:SU(2):   SW %1:gpr, %0:gpr, 12 :: (store 4 into %ir.arrayidx)
17; CHECK-NOT: Successors:
18; CHECK:SU(3):   SW %1:gpr, %0:gpr, 8 :: (store 4 into %ir.arrayidx1)
19; CHECK: Predecessors:
20; CHECK-NOT:    SU(2): Ord  Latency=0 Memory
21  %arrayidx = getelementptr inbounds i32, i32* %P, i32 3
22  store i32 %v, i32* %arrayidx
23  %arrayidx1 = getelementptr inbounds i32, i32* %P, i32 2
24  store i32 %v, i32* %arrayidx1
25  ret i32 %v
26}
27