1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV32IFD %s
6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV64I %s
8; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64IFD %s
10;
11; This file tests cases where simple floating point operations can be
12; profitably handled though bit manipulation if a soft-float ABI is being used
13; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
14; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
15; in cases where we perform custom legalisation (e.g. RV32IFD).
16
17; TODO: Add an appropriate target-specific DAG combine that can handle
18; RISCVISD::SplitF64/BuildPairF64 used for RV32IFD.
19
20define double @fneg(double %a) nounwind {
21; RV32I-LABEL: fneg:
22; RV32I:       # %bb.0:
23; RV32I-NEXT:    lui a2, 524288
24; RV32I-NEXT:    xor a1, a1, a2
25; RV32I-NEXT:    ret
26;
27; RV32IFD-LABEL: fneg:
28; RV32IFD:       # %bb.0:
29; RV32IFD-NEXT:    lui a2, 524288
30; RV32IFD-NEXT:    xor a1, a1, a2
31; RV32IFD-NEXT:    ret
32;
33; RV64I-LABEL: fneg:
34; RV64I:       # %bb.0:
35; RV64I-NEXT:    addi a1, zero, -1
36; RV64I-NEXT:    slli a1, a1, 63
37; RV64I-NEXT:    xor a0, a0, a1
38; RV64I-NEXT:    ret
39;
40; RV64IFD-LABEL: fneg:
41; RV64IFD:       # %bb.0:
42; RV64IFD-NEXT:    addi a1, zero, -1
43; RV64IFD-NEXT:    slli a1, a1, 63
44; RV64IFD-NEXT:    xor a0, a0, a1
45; RV64IFD-NEXT:    ret
46  %1 = fneg double %a
47  ret double %1
48}
49
50declare double @llvm.fabs.f64(double)
51
52define double @fabs(double %a) nounwind {
53; RV32I-LABEL: fabs:
54; RV32I:       # %bb.0:
55; RV32I-NEXT:    lui a2, 524288
56; RV32I-NEXT:    addi a2, a2, -1
57; RV32I-NEXT:    and a1, a1, a2
58; RV32I-NEXT:    ret
59;
60; RV32IFD-LABEL: fabs:
61; RV32IFD:       # %bb.0:
62; RV32IFD-NEXT:    lui a2, 524288
63; RV32IFD-NEXT:    addi a2, a2, -1
64; RV32IFD-NEXT:    and a1, a1, a2
65; RV32IFD-NEXT:    ret
66;
67; RV64I-LABEL: fabs:
68; RV64I:       # %bb.0:
69; RV64I-NEXT:    addi a1, zero, -1
70; RV64I-NEXT:    slli a1, a1, 63
71; RV64I-NEXT:    addi a1, a1, -1
72; RV64I-NEXT:    and a0, a0, a1
73; RV64I-NEXT:    ret
74;
75; RV64IFD-LABEL: fabs:
76; RV64IFD:       # %bb.0:
77; RV64IFD-NEXT:    addi a1, zero, -1
78; RV64IFD-NEXT:    slli a1, a1, 63
79; RV64IFD-NEXT:    addi a1, a1, -1
80; RV64IFD-NEXT:    and a0, a0, a1
81; RV64IFD-NEXT:    ret
82  %1 = call double @llvm.fabs.f64(double %a)
83  ret double %1
84}
85
86declare double @llvm.copysign.f64(double, double)
87
88; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
89; operations if floating point isn't supported. A combine could be written to
90; do the same even when f64 is legal.
91
92define double @fcopysign_fneg(double %a, double %b) nounwind {
93; RV32I-LABEL: fcopysign_fneg:
94; RV32I:       # %bb.0:
95; RV32I-NEXT:    not a2, a3
96; RV32I-NEXT:    lui a3, 524288
97; RV32I-NEXT:    and a2, a2, a3
98; RV32I-NEXT:    addi a3, a3, -1
99; RV32I-NEXT:    and a1, a1, a3
100; RV32I-NEXT:    or a1, a1, a2
101; RV32I-NEXT:    ret
102;
103; RV32IFD-LABEL: fcopysign_fneg:
104; RV32IFD:       # %bb.0:
105; RV32IFD-NEXT:    addi sp, sp, -16
106; RV32IFD-NEXT:    sw a2, 8(sp)
107; RV32IFD-NEXT:    sw a3, 12(sp)
108; RV32IFD-NEXT:    fld ft0, 8(sp)
109; RV32IFD-NEXT:    sw a0, 8(sp)
110; RV32IFD-NEXT:    sw a1, 12(sp)
111; RV32IFD-NEXT:    fld ft1, 8(sp)
112; RV32IFD-NEXT:    fsgnjn.d ft0, ft1, ft0
113; RV32IFD-NEXT:    fsd ft0, 8(sp)
114; RV32IFD-NEXT:    lw a0, 8(sp)
115; RV32IFD-NEXT:    lw a1, 12(sp)
116; RV32IFD-NEXT:    addi sp, sp, 16
117; RV32IFD-NEXT:    ret
118;
119; RV64I-LABEL: fcopysign_fneg:
120; RV64I:       # %bb.0:
121; RV64I-NEXT:    not a1, a1
122; RV64I-NEXT:    addi a2, zero, -1
123; RV64I-NEXT:    slli a2, a2, 63
124; RV64I-NEXT:    and a1, a1, a2
125; RV64I-NEXT:    addi a2, a2, -1
126; RV64I-NEXT:    and a0, a0, a2
127; RV64I-NEXT:    or a0, a0, a1
128; RV64I-NEXT:    ret
129;
130; RV64IFD-LABEL: fcopysign_fneg:
131; RV64IFD:       # %bb.0:
132; RV64IFD-NEXT:    addi a2, zero, -1
133; RV64IFD-NEXT:    slli a2, a2, 63
134; RV64IFD-NEXT:    xor a1, a1, a2
135; RV64IFD-NEXT:    fmv.d.x ft0, a1
136; RV64IFD-NEXT:    fmv.d.x ft1, a0
137; RV64IFD-NEXT:    fsgnj.d ft0, ft1, ft0
138; RV64IFD-NEXT:    fmv.x.d a0, ft0
139; RV64IFD-NEXT:    ret
140  %1 = fneg double %b
141  %2 = call double @llvm.copysign.f64(double %a, double %1)
142  ret double %2
143}
144