1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
3; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
5; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
6
7define zeroext i1 @float_is_nan(float %a) nounwind {
8; RV32IF-LABEL: float_is_nan:
9; RV32IF:       # %bb.0:
10; RV32IF-NEXT:    feq.s a0, fa0, fa0
11; RV32IF-NEXT:    seqz a0, a0
12; RV32IF-NEXT:    ret
13;
14; RV64IF-LABEL: float_is_nan:
15; RV64IF:       # %bb.0:
16; RV64IF-NEXT:    feq.s a0, fa0, fa0
17; RV64IF-NEXT:    seqz a0, a0
18; RV64IF-NEXT:    ret
19  %1 = fcmp uno float %a, 0.000000e+00
20  ret i1 %1
21}
22
23define zeroext i1 @float_not_nan(float %a) nounwind {
24; RV32IF-LABEL: float_not_nan:
25; RV32IF:       # %bb.0:
26; RV32IF-NEXT:    feq.s a0, fa0, fa0
27; RV32IF-NEXT:    ret
28;
29; RV64IF-LABEL: float_not_nan:
30; RV64IF:       # %bb.0:
31; RV64IF-NEXT:    feq.s a0, fa0, fa0
32; RV64IF-NEXT:    ret
33  %1 = fcmp ord float %a, 0.000000e+00
34  ret i1 %1
35}
36