1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
6
7declare void @abort()
8declare void @exit(i32)
9declare half @dummy(half)
10
11define void @br_fcmp_false(half %a, half %b) nounwind {
12; RV32IZFH-LABEL: br_fcmp_false:
13; RV32IZFH:       # %bb.0:
14; RV32IZFH-NEXT:    addi sp, sp, -16
15; RV32IZFH-NEXT:    sw ra, 12(sp)
16; RV32IZFH-NEXT:    addi a0, zero, 1
17; RV32IZFH-NEXT:    bnez a0, .LBB0_2
18; RV32IZFH-NEXT:  # %bb.1: # %if.then
19; RV32IZFH-NEXT:    lw ra, 12(sp)
20; RV32IZFH-NEXT:    addi sp, sp, 16
21; RV32IZFH-NEXT:    ret
22; RV32IZFH-NEXT:  .LBB0_2: # %if.else
23; RV32IZFH-NEXT:    call abort
24;
25; RV64IZFH-LABEL: br_fcmp_false:
26; RV64IZFH:       # %bb.0:
27; RV64IZFH-NEXT:    addi sp, sp, -16
28; RV64IZFH-NEXT:    sd ra, 8(sp)
29; RV64IZFH-NEXT:    addi a0, zero, 1
30; RV64IZFH-NEXT:    bnez a0, .LBB0_2
31; RV64IZFH-NEXT:  # %bb.1: # %if.then
32; RV64IZFH-NEXT:    ld ra, 8(sp)
33; RV64IZFH-NEXT:    addi sp, sp, 16
34; RV64IZFH-NEXT:    ret
35; RV64IZFH-NEXT:  .LBB0_2: # %if.else
36; RV64IZFH-NEXT:    call abort
37  %1 = fcmp false half %a, %b
38  br i1 %1, label %if.then, label %if.else
39if.then:
40  ret void
41if.else:
42  tail call void @abort()
43  unreachable
44}
45
46define void @br_fcmp_oeq(half %a, half %b) nounwind {
47; RV32IZFH-LABEL: br_fcmp_oeq:
48; RV32IZFH:       # %bb.0:
49; RV32IZFH-NEXT:    addi sp, sp, -16
50; RV32IZFH-NEXT:    sw ra, 12(sp)
51; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
52; RV32IZFH-NEXT:    bnez a0, .LBB1_2
53; RV32IZFH-NEXT:  # %bb.1: # %if.else
54; RV32IZFH-NEXT:    lw ra, 12(sp)
55; RV32IZFH-NEXT:    addi sp, sp, 16
56; RV32IZFH-NEXT:    ret
57; RV32IZFH-NEXT:  .LBB1_2: # %if.then
58; RV32IZFH-NEXT:    call abort
59;
60; RV64IZFH-LABEL: br_fcmp_oeq:
61; RV64IZFH:       # %bb.0:
62; RV64IZFH-NEXT:    addi sp, sp, -16
63; RV64IZFH-NEXT:    sd ra, 8(sp)
64; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
65; RV64IZFH-NEXT:    bnez a0, .LBB1_2
66; RV64IZFH-NEXT:  # %bb.1: # %if.else
67; RV64IZFH-NEXT:    ld ra, 8(sp)
68; RV64IZFH-NEXT:    addi sp, sp, 16
69; RV64IZFH-NEXT:    ret
70; RV64IZFH-NEXT:  .LBB1_2: # %if.then
71; RV64IZFH-NEXT:    call abort
72  %1 = fcmp oeq half %a, %b
73  br i1 %1, label %if.then, label %if.else
74if.else:
75  ret void
76if.then:
77  tail call void @abort()
78  unreachable
79}
80
81; TODO: generated code quality for this is very poor due to
82; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
83; expansion.
84define void @br_fcmp_oeq_alt(half %a, half %b) nounwind {
85; RV32IZFH-LABEL: br_fcmp_oeq_alt:
86; RV32IZFH:       # %bb.0:
87; RV32IZFH-NEXT:    addi sp, sp, -16
88; RV32IZFH-NEXT:    sw ra, 12(sp)
89; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
90; RV32IZFH-NEXT:    xori a0, a0, 1
91; RV32IZFH-NEXT:    beqz a0, .LBB2_2
92; RV32IZFH-NEXT:  # %bb.1: # %if.else
93; RV32IZFH-NEXT:    lw ra, 12(sp)
94; RV32IZFH-NEXT:    addi sp, sp, 16
95; RV32IZFH-NEXT:    ret
96; RV32IZFH-NEXT:  .LBB2_2: # %if.then
97; RV32IZFH-NEXT:    call abort
98;
99; RV64IZFH-LABEL: br_fcmp_oeq_alt:
100; RV64IZFH:       # %bb.0:
101; RV64IZFH-NEXT:    addi sp, sp, -16
102; RV64IZFH-NEXT:    sd ra, 8(sp)
103; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
104; RV64IZFH-NEXT:    xori a0, a0, 1
105; RV64IZFH-NEXT:    beqz a0, .LBB2_2
106; RV64IZFH-NEXT:  # %bb.1: # %if.else
107; RV64IZFH-NEXT:    ld ra, 8(sp)
108; RV64IZFH-NEXT:    addi sp, sp, 16
109; RV64IZFH-NEXT:    ret
110; RV64IZFH-NEXT:  .LBB2_2: # %if.then
111; RV64IZFH-NEXT:    call abort
112  %1 = fcmp oeq half %a, %b
113  br i1 %1, label %if.then, label %if.else
114if.then:
115  tail call void @abort()
116  unreachable
117if.else:
118  ret void
119}
120
121define void @br_fcmp_ogt(half %a, half %b) nounwind {
122; RV32IZFH-LABEL: br_fcmp_ogt:
123; RV32IZFH:       # %bb.0:
124; RV32IZFH-NEXT:    addi sp, sp, -16
125; RV32IZFH-NEXT:    sw ra, 12(sp)
126; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
127; RV32IZFH-NEXT:    bnez a0, .LBB3_2
128; RV32IZFH-NEXT:  # %bb.1: # %if.else
129; RV32IZFH-NEXT:    lw ra, 12(sp)
130; RV32IZFH-NEXT:    addi sp, sp, 16
131; RV32IZFH-NEXT:    ret
132; RV32IZFH-NEXT:  .LBB3_2: # %if.then
133; RV32IZFH-NEXT:    call abort
134;
135; RV64IZFH-LABEL: br_fcmp_ogt:
136; RV64IZFH:       # %bb.0:
137; RV64IZFH-NEXT:    addi sp, sp, -16
138; RV64IZFH-NEXT:    sd ra, 8(sp)
139; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
140; RV64IZFH-NEXT:    bnez a0, .LBB3_2
141; RV64IZFH-NEXT:  # %bb.1: # %if.else
142; RV64IZFH-NEXT:    ld ra, 8(sp)
143; RV64IZFH-NEXT:    addi sp, sp, 16
144; RV64IZFH-NEXT:    ret
145; RV64IZFH-NEXT:  .LBB3_2: # %if.then
146; RV64IZFH-NEXT:    call abort
147  %1 = fcmp ogt half %a, %b
148  br i1 %1, label %if.then, label %if.else
149if.else:
150  ret void
151if.then:
152  tail call void @abort()
153  unreachable
154}
155
156define void @br_fcmp_oge(half %a, half %b) nounwind {
157; RV32IZFH-LABEL: br_fcmp_oge:
158; RV32IZFH:       # %bb.0:
159; RV32IZFH-NEXT:    addi sp, sp, -16
160; RV32IZFH-NEXT:    sw ra, 12(sp)
161; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
162; RV32IZFH-NEXT:    bnez a0, .LBB4_2
163; RV32IZFH-NEXT:  # %bb.1: # %if.else
164; RV32IZFH-NEXT:    lw ra, 12(sp)
165; RV32IZFH-NEXT:    addi sp, sp, 16
166; RV32IZFH-NEXT:    ret
167; RV32IZFH-NEXT:  .LBB4_2: # %if.then
168; RV32IZFH-NEXT:    call abort
169;
170; RV64IZFH-LABEL: br_fcmp_oge:
171; RV64IZFH:       # %bb.0:
172; RV64IZFH-NEXT:    addi sp, sp, -16
173; RV64IZFH-NEXT:    sd ra, 8(sp)
174; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
175; RV64IZFH-NEXT:    bnez a0, .LBB4_2
176; RV64IZFH-NEXT:  # %bb.1: # %if.else
177; RV64IZFH-NEXT:    ld ra, 8(sp)
178; RV64IZFH-NEXT:    addi sp, sp, 16
179; RV64IZFH-NEXT:    ret
180; RV64IZFH-NEXT:  .LBB4_2: # %if.then
181; RV64IZFH-NEXT:    call abort
182  %1 = fcmp oge half %a, %b
183  br i1 %1, label %if.then, label %if.else
184if.else:
185  ret void
186if.then:
187  tail call void @abort()
188  unreachable
189}
190
191define void @br_fcmp_olt(half %a, half %b) nounwind {
192; RV32IZFH-LABEL: br_fcmp_olt:
193; RV32IZFH:       # %bb.0:
194; RV32IZFH-NEXT:    addi sp, sp, -16
195; RV32IZFH-NEXT:    sw ra, 12(sp)
196; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
197; RV32IZFH-NEXT:    bnez a0, .LBB5_2
198; RV32IZFH-NEXT:  # %bb.1: # %if.else
199; RV32IZFH-NEXT:    lw ra, 12(sp)
200; RV32IZFH-NEXT:    addi sp, sp, 16
201; RV32IZFH-NEXT:    ret
202; RV32IZFH-NEXT:  .LBB5_2: # %if.then
203; RV32IZFH-NEXT:    call abort
204;
205; RV64IZFH-LABEL: br_fcmp_olt:
206; RV64IZFH:       # %bb.0:
207; RV64IZFH-NEXT:    addi sp, sp, -16
208; RV64IZFH-NEXT:    sd ra, 8(sp)
209; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
210; RV64IZFH-NEXT:    bnez a0, .LBB5_2
211; RV64IZFH-NEXT:  # %bb.1: # %if.else
212; RV64IZFH-NEXT:    ld ra, 8(sp)
213; RV64IZFH-NEXT:    addi sp, sp, 16
214; RV64IZFH-NEXT:    ret
215; RV64IZFH-NEXT:  .LBB5_2: # %if.then
216; RV64IZFH-NEXT:    call abort
217  %1 = fcmp olt half %a, %b
218  br i1 %1, label %if.then, label %if.else
219if.else:
220  ret void
221if.then:
222  tail call void @abort()
223  unreachable
224}
225
226define void @br_fcmp_ole(half %a, half %b) nounwind {
227; RV32IZFH-LABEL: br_fcmp_ole:
228; RV32IZFH:       # %bb.0:
229; RV32IZFH-NEXT:    addi sp, sp, -16
230; RV32IZFH-NEXT:    sw ra, 12(sp)
231; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
232; RV32IZFH-NEXT:    bnez a0, .LBB6_2
233; RV32IZFH-NEXT:  # %bb.1: # %if.else
234; RV32IZFH-NEXT:    lw ra, 12(sp)
235; RV32IZFH-NEXT:    addi sp, sp, 16
236; RV32IZFH-NEXT:    ret
237; RV32IZFH-NEXT:  .LBB6_2: # %if.then
238; RV32IZFH-NEXT:    call abort
239;
240; RV64IZFH-LABEL: br_fcmp_ole:
241; RV64IZFH:       # %bb.0:
242; RV64IZFH-NEXT:    addi sp, sp, -16
243; RV64IZFH-NEXT:    sd ra, 8(sp)
244; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
245; RV64IZFH-NEXT:    bnez a0, .LBB6_2
246; RV64IZFH-NEXT:  # %bb.1: # %if.else
247; RV64IZFH-NEXT:    ld ra, 8(sp)
248; RV64IZFH-NEXT:    addi sp, sp, 16
249; RV64IZFH-NEXT:    ret
250; RV64IZFH-NEXT:  .LBB6_2: # %if.then
251; RV64IZFH-NEXT:    call abort
252  %1 = fcmp ole half %a, %b
253  br i1 %1, label %if.then, label %if.else
254if.else:
255  ret void
256if.then:
257  tail call void @abort()
258  unreachable
259}
260
261; TODO: feq.h+sltiu+bne -> feq.h+beq
262define void @br_fcmp_one(half %a, half %b) nounwind {
263; RV32IZFH-LABEL: br_fcmp_one:
264; RV32IZFH:       # %bb.0:
265; RV32IZFH-NEXT:    addi sp, sp, -16
266; RV32IZFH-NEXT:    sw ra, 12(sp)
267; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
268; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
269; RV32IZFH-NEXT:    and a0, a1, a0
270; RV32IZFH-NEXT:    feq.h a1, fa0, fa1
271; RV32IZFH-NEXT:    not a1, a1
272; RV32IZFH-NEXT:    and a0, a1, a0
273; RV32IZFH-NEXT:    bnez a0, .LBB7_2
274; RV32IZFH-NEXT:  # %bb.1: # %if.else
275; RV32IZFH-NEXT:    lw ra, 12(sp)
276; RV32IZFH-NEXT:    addi sp, sp, 16
277; RV32IZFH-NEXT:    ret
278; RV32IZFH-NEXT:  .LBB7_2: # %if.then
279; RV32IZFH-NEXT:    call abort
280;
281; RV64IZFH-LABEL: br_fcmp_one:
282; RV64IZFH:       # %bb.0:
283; RV64IZFH-NEXT:    addi sp, sp, -16
284; RV64IZFH-NEXT:    sd ra, 8(sp)
285; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
286; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
287; RV64IZFH-NEXT:    and a0, a1, a0
288; RV64IZFH-NEXT:    feq.h a1, fa0, fa1
289; RV64IZFH-NEXT:    not a1, a1
290; RV64IZFH-NEXT:    and a0, a1, a0
291; RV64IZFH-NEXT:    bnez a0, .LBB7_2
292; RV64IZFH-NEXT:  # %bb.1: # %if.else
293; RV64IZFH-NEXT:    ld ra, 8(sp)
294; RV64IZFH-NEXT:    addi sp, sp, 16
295; RV64IZFH-NEXT:    ret
296; RV64IZFH-NEXT:  .LBB7_2: # %if.then
297; RV64IZFH-NEXT:    call abort
298  %1 = fcmp one half %a, %b
299  br i1 %1, label %if.then, label %if.else
300if.else:
301  ret void
302if.then:
303  tail call void @abort()
304  unreachable
305}
306
307define void @br_fcmp_ord(half %a, half %b) nounwind {
308; RV32IZFH-LABEL: br_fcmp_ord:
309; RV32IZFH:       # %bb.0:
310; RV32IZFH-NEXT:    addi sp, sp, -16
311; RV32IZFH-NEXT:    sw ra, 12(sp)
312; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
313; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
314; RV32IZFH-NEXT:    and a0, a1, a0
315; RV32IZFH-NEXT:    bnez a0, .LBB8_2
316; RV32IZFH-NEXT:  # %bb.1: # %if.else
317; RV32IZFH-NEXT:    lw ra, 12(sp)
318; RV32IZFH-NEXT:    addi sp, sp, 16
319; RV32IZFH-NEXT:    ret
320; RV32IZFH-NEXT:  .LBB8_2: # %if.then
321; RV32IZFH-NEXT:    call abort
322;
323; RV64IZFH-LABEL: br_fcmp_ord:
324; RV64IZFH:       # %bb.0:
325; RV64IZFH-NEXT:    addi sp, sp, -16
326; RV64IZFH-NEXT:    sd ra, 8(sp)
327; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
328; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
329; RV64IZFH-NEXT:    and a0, a1, a0
330; RV64IZFH-NEXT:    bnez a0, .LBB8_2
331; RV64IZFH-NEXT:  # %bb.1: # %if.else
332; RV64IZFH-NEXT:    ld ra, 8(sp)
333; RV64IZFH-NEXT:    addi sp, sp, 16
334; RV64IZFH-NEXT:    ret
335; RV64IZFH-NEXT:  .LBB8_2: # %if.then
336; RV64IZFH-NEXT:    call abort
337  %1 = fcmp ord half %a, %b
338  br i1 %1, label %if.then, label %if.else
339if.else:
340  ret void
341if.then:
342  tail call void @abort()
343  unreachable
344}
345
346define void @br_fcmp_ueq(half %a, half %b) nounwind {
347; RV32IZFH-LABEL: br_fcmp_ueq:
348; RV32IZFH:       # %bb.0:
349; RV32IZFH-NEXT:    addi sp, sp, -16
350; RV32IZFH-NEXT:    sw ra, 12(sp)
351; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
352; RV32IZFH-NEXT:    feq.h a1, fa1, fa1
353; RV32IZFH-NEXT:    feq.h a2, fa0, fa0
354; RV32IZFH-NEXT:    and a1, a2, a1
355; RV32IZFH-NEXT:    seqz a1, a1
356; RV32IZFH-NEXT:    or a0, a0, a1
357; RV32IZFH-NEXT:    bnez a0, .LBB9_2
358; RV32IZFH-NEXT:  # %bb.1: # %if.else
359; RV32IZFH-NEXT:    lw ra, 12(sp)
360; RV32IZFH-NEXT:    addi sp, sp, 16
361; RV32IZFH-NEXT:    ret
362; RV32IZFH-NEXT:  .LBB9_2: # %if.then
363; RV32IZFH-NEXT:    call abort
364;
365; RV64IZFH-LABEL: br_fcmp_ueq:
366; RV64IZFH:       # %bb.0:
367; RV64IZFH-NEXT:    addi sp, sp, -16
368; RV64IZFH-NEXT:    sd ra, 8(sp)
369; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
370; RV64IZFH-NEXT:    feq.h a1, fa1, fa1
371; RV64IZFH-NEXT:    feq.h a2, fa0, fa0
372; RV64IZFH-NEXT:    and a1, a2, a1
373; RV64IZFH-NEXT:    seqz a1, a1
374; RV64IZFH-NEXT:    or a0, a0, a1
375; RV64IZFH-NEXT:    bnez a0, .LBB9_2
376; RV64IZFH-NEXT:  # %bb.1: # %if.else
377; RV64IZFH-NEXT:    ld ra, 8(sp)
378; RV64IZFH-NEXT:    addi sp, sp, 16
379; RV64IZFH-NEXT:    ret
380; RV64IZFH-NEXT:  .LBB9_2: # %if.then
381; RV64IZFH-NEXT:    call abort
382  %1 = fcmp ueq half %a, %b
383  br i1 %1, label %if.then, label %if.else
384if.else:
385  ret void
386if.then:
387  tail call void @abort()
388  unreachable
389}
390
391define void @br_fcmp_ugt(half %a, half %b) nounwind {
392; RV32IZFH-LABEL: br_fcmp_ugt:
393; RV32IZFH:       # %bb.0:
394; RV32IZFH-NEXT:    addi sp, sp, -16
395; RV32IZFH-NEXT:    sw ra, 12(sp)
396; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
397; RV32IZFH-NEXT:    xori a0, a0, 1
398; RV32IZFH-NEXT:    bnez a0, .LBB10_2
399; RV32IZFH-NEXT:  # %bb.1: # %if.else
400; RV32IZFH-NEXT:    lw ra, 12(sp)
401; RV32IZFH-NEXT:    addi sp, sp, 16
402; RV32IZFH-NEXT:    ret
403; RV32IZFH-NEXT:  .LBB10_2: # %if.then
404; RV32IZFH-NEXT:    call abort
405;
406; RV64IZFH-LABEL: br_fcmp_ugt:
407; RV64IZFH:       # %bb.0:
408; RV64IZFH-NEXT:    addi sp, sp, -16
409; RV64IZFH-NEXT:    sd ra, 8(sp)
410; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
411; RV64IZFH-NEXT:    xori a0, a0, 1
412; RV64IZFH-NEXT:    bnez a0, .LBB10_2
413; RV64IZFH-NEXT:  # %bb.1: # %if.else
414; RV64IZFH-NEXT:    ld ra, 8(sp)
415; RV64IZFH-NEXT:    addi sp, sp, 16
416; RV64IZFH-NEXT:    ret
417; RV64IZFH-NEXT:  .LBB10_2: # %if.then
418; RV64IZFH-NEXT:    call abort
419  %1 = fcmp ugt half %a, %b
420  br i1 %1, label %if.then, label %if.else
421if.else:
422  ret void
423if.then:
424  tail call void @abort()
425  unreachable
426}
427
428define void @br_fcmp_uge(half %a, half %b) nounwind {
429; RV32IZFH-LABEL: br_fcmp_uge:
430; RV32IZFH:       # %bb.0:
431; RV32IZFH-NEXT:    addi sp, sp, -16
432; RV32IZFH-NEXT:    sw ra, 12(sp)
433; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
434; RV32IZFH-NEXT:    xori a0, a0, 1
435; RV32IZFH-NEXT:    bnez a0, .LBB11_2
436; RV32IZFH-NEXT:  # %bb.1: # %if.else
437; RV32IZFH-NEXT:    lw ra, 12(sp)
438; RV32IZFH-NEXT:    addi sp, sp, 16
439; RV32IZFH-NEXT:    ret
440; RV32IZFH-NEXT:  .LBB11_2: # %if.then
441; RV32IZFH-NEXT:    call abort
442;
443; RV64IZFH-LABEL: br_fcmp_uge:
444; RV64IZFH:       # %bb.0:
445; RV64IZFH-NEXT:    addi sp, sp, -16
446; RV64IZFH-NEXT:    sd ra, 8(sp)
447; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
448; RV64IZFH-NEXT:    xori a0, a0, 1
449; RV64IZFH-NEXT:    bnez a0, .LBB11_2
450; RV64IZFH-NEXT:  # %bb.1: # %if.else
451; RV64IZFH-NEXT:    ld ra, 8(sp)
452; RV64IZFH-NEXT:    addi sp, sp, 16
453; RV64IZFH-NEXT:    ret
454; RV64IZFH-NEXT:  .LBB11_2: # %if.then
455; RV64IZFH-NEXT:    call abort
456  %1 = fcmp uge half %a, %b
457  br i1 %1, label %if.then, label %if.else
458if.else:
459  ret void
460if.then:
461  tail call void @abort()
462  unreachable
463}
464
465define void @br_fcmp_ult(half %a, half %b) nounwind {
466; RV32IZFH-LABEL: br_fcmp_ult:
467; RV32IZFH:       # %bb.0:
468; RV32IZFH-NEXT:    addi sp, sp, -16
469; RV32IZFH-NEXT:    sw ra, 12(sp)
470; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
471; RV32IZFH-NEXT:    xori a0, a0, 1
472; RV32IZFH-NEXT:    bnez a0, .LBB12_2
473; RV32IZFH-NEXT:  # %bb.1: # %if.else
474; RV32IZFH-NEXT:    lw ra, 12(sp)
475; RV32IZFH-NEXT:    addi sp, sp, 16
476; RV32IZFH-NEXT:    ret
477; RV32IZFH-NEXT:  .LBB12_2: # %if.then
478; RV32IZFH-NEXT:    call abort
479;
480; RV64IZFH-LABEL: br_fcmp_ult:
481; RV64IZFH:       # %bb.0:
482; RV64IZFH-NEXT:    addi sp, sp, -16
483; RV64IZFH-NEXT:    sd ra, 8(sp)
484; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
485; RV64IZFH-NEXT:    xori a0, a0, 1
486; RV64IZFH-NEXT:    bnez a0, .LBB12_2
487; RV64IZFH-NEXT:  # %bb.1: # %if.else
488; RV64IZFH-NEXT:    ld ra, 8(sp)
489; RV64IZFH-NEXT:    addi sp, sp, 16
490; RV64IZFH-NEXT:    ret
491; RV64IZFH-NEXT:  .LBB12_2: # %if.then
492; RV64IZFH-NEXT:    call abort
493  %1 = fcmp ult half %a, %b
494  br i1 %1, label %if.then, label %if.else
495if.else:
496  ret void
497if.then:
498  tail call void @abort()
499  unreachable
500}
501
502define void @br_fcmp_ule(half %a, half %b) nounwind {
503; RV32IZFH-LABEL: br_fcmp_ule:
504; RV32IZFH:       # %bb.0:
505; RV32IZFH-NEXT:    addi sp, sp, -16
506; RV32IZFH-NEXT:    sw ra, 12(sp)
507; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
508; RV32IZFH-NEXT:    xori a0, a0, 1
509; RV32IZFH-NEXT:    bnez a0, .LBB13_2
510; RV32IZFH-NEXT:  # %bb.1: # %if.else
511; RV32IZFH-NEXT:    lw ra, 12(sp)
512; RV32IZFH-NEXT:    addi sp, sp, 16
513; RV32IZFH-NEXT:    ret
514; RV32IZFH-NEXT:  .LBB13_2: # %if.then
515; RV32IZFH-NEXT:    call abort
516;
517; RV64IZFH-LABEL: br_fcmp_ule:
518; RV64IZFH:       # %bb.0:
519; RV64IZFH-NEXT:    addi sp, sp, -16
520; RV64IZFH-NEXT:    sd ra, 8(sp)
521; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
522; RV64IZFH-NEXT:    xori a0, a0, 1
523; RV64IZFH-NEXT:    bnez a0, .LBB13_2
524; RV64IZFH-NEXT:  # %bb.1: # %if.else
525; RV64IZFH-NEXT:    ld ra, 8(sp)
526; RV64IZFH-NEXT:    addi sp, sp, 16
527; RV64IZFH-NEXT:    ret
528; RV64IZFH-NEXT:  .LBB13_2: # %if.then
529; RV64IZFH-NEXT:    call abort
530  %1 = fcmp ule half %a, %b
531  br i1 %1, label %if.then, label %if.else
532if.else:
533  ret void
534if.then:
535  tail call void @abort()
536  unreachable
537}
538
539define void @br_fcmp_une(half %a, half %b) nounwind {
540; RV32IZFH-LABEL: br_fcmp_une:
541; RV32IZFH:       # %bb.0:
542; RV32IZFH-NEXT:    addi sp, sp, -16
543; RV32IZFH-NEXT:    sw ra, 12(sp)
544; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
545; RV32IZFH-NEXT:    xori a0, a0, 1
546; RV32IZFH-NEXT:    bnez a0, .LBB14_2
547; RV32IZFH-NEXT:  # %bb.1: # %if.else
548; RV32IZFH-NEXT:    lw ra, 12(sp)
549; RV32IZFH-NEXT:    addi sp, sp, 16
550; RV32IZFH-NEXT:    ret
551; RV32IZFH-NEXT:  .LBB14_2: # %if.then
552; RV32IZFH-NEXT:    call abort
553;
554; RV64IZFH-LABEL: br_fcmp_une:
555; RV64IZFH:       # %bb.0:
556; RV64IZFH-NEXT:    addi sp, sp, -16
557; RV64IZFH-NEXT:    sd ra, 8(sp)
558; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
559; RV64IZFH-NEXT:    xori a0, a0, 1
560; RV64IZFH-NEXT:    bnez a0, .LBB14_2
561; RV64IZFH-NEXT:  # %bb.1: # %if.else
562; RV64IZFH-NEXT:    ld ra, 8(sp)
563; RV64IZFH-NEXT:    addi sp, sp, 16
564; RV64IZFH-NEXT:    ret
565; RV64IZFH-NEXT:  .LBB14_2: # %if.then
566; RV64IZFH-NEXT:    call abort
567  %1 = fcmp une half %a, %b
568  br i1 %1, label %if.then, label %if.else
569if.else:
570  ret void
571if.then:
572  tail call void @abort()
573  unreachable
574}
575
576define void @br_fcmp_uno(half %a, half %b) nounwind {
577; TODO: sltiu+bne -> beq
578; RV32IZFH-LABEL: br_fcmp_uno:
579; RV32IZFH:       # %bb.0:
580; RV32IZFH-NEXT:    addi sp, sp, -16
581; RV32IZFH-NEXT:    sw ra, 12(sp)
582; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
583; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
584; RV32IZFH-NEXT:    and a0, a1, a0
585; RV32IZFH-NEXT:    seqz a0, a0
586; RV32IZFH-NEXT:    bnez a0, .LBB15_2
587; RV32IZFH-NEXT:  # %bb.1: # %if.else
588; RV32IZFH-NEXT:    lw ra, 12(sp)
589; RV32IZFH-NEXT:    addi sp, sp, 16
590; RV32IZFH-NEXT:    ret
591; RV32IZFH-NEXT:  .LBB15_2: # %if.then
592; RV32IZFH-NEXT:    call abort
593;
594; RV64IZFH-LABEL: br_fcmp_uno:
595; RV64IZFH:       # %bb.0:
596; RV64IZFH-NEXT:    addi sp, sp, -16
597; RV64IZFH-NEXT:    sd ra, 8(sp)
598; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
599; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
600; RV64IZFH-NEXT:    and a0, a1, a0
601; RV64IZFH-NEXT:    seqz a0, a0
602; RV64IZFH-NEXT:    bnez a0, .LBB15_2
603; RV64IZFH-NEXT:  # %bb.1: # %if.else
604; RV64IZFH-NEXT:    ld ra, 8(sp)
605; RV64IZFH-NEXT:    addi sp, sp, 16
606; RV64IZFH-NEXT:    ret
607; RV64IZFH-NEXT:  .LBB15_2: # %if.then
608; RV64IZFH-NEXT:    call abort
609  %1 = fcmp uno half %a, %b
610  br i1 %1, label %if.then, label %if.else
611if.else:
612  ret void
613if.then:
614  tail call void @abort()
615  unreachable
616}
617
618define void @br_fcmp_true(half %a, half %b) nounwind {
619; RV32IZFH-LABEL: br_fcmp_true:
620; RV32IZFH:       # %bb.0:
621; RV32IZFH-NEXT:    addi sp, sp, -16
622; RV32IZFH-NEXT:    sw ra, 12(sp)
623; RV32IZFH-NEXT:    addi a0, zero, 1
624; RV32IZFH-NEXT:    bnez a0, .LBB16_2
625; RV32IZFH-NEXT:  # %bb.1: # %if.else
626; RV32IZFH-NEXT:    lw ra, 12(sp)
627; RV32IZFH-NEXT:    addi sp, sp, 16
628; RV32IZFH-NEXT:    ret
629; RV32IZFH-NEXT:  .LBB16_2: # %if.then
630; RV32IZFH-NEXT:    call abort
631;
632; RV64IZFH-LABEL: br_fcmp_true:
633; RV64IZFH:       # %bb.0:
634; RV64IZFH-NEXT:    addi sp, sp, -16
635; RV64IZFH-NEXT:    sd ra, 8(sp)
636; RV64IZFH-NEXT:    addi a0, zero, 1
637; RV64IZFH-NEXT:    bnez a0, .LBB16_2
638; RV64IZFH-NEXT:  # %bb.1: # %if.else
639; RV64IZFH-NEXT:    ld ra, 8(sp)
640; RV64IZFH-NEXT:    addi sp, sp, 16
641; RV64IZFH-NEXT:    ret
642; RV64IZFH-NEXT:  .LBB16_2: # %if.then
643; RV64IZFH-NEXT:    call abort
644  %1 = fcmp true half %a, %b
645  br i1 %1, label %if.then, label %if.else
646if.else:
647  ret void
648if.then:
649  tail call void @abort()
650  unreachable
651}
652