1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
6
7define zeroext i1 @half_is_nan(half %a) nounwind {
8; RV32IZFH-LABEL: half_is_nan:
9; RV32IZFH:       # %bb.0:
10; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
11; RV32IZFH-NEXT:    seqz a0, a0
12; RV32IZFH-NEXT:    ret
13;
14; RV64IZFH-LABEL: half_is_nan:
15; RV64IZFH:       # %bb.0:
16; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
17; RV64IZFH-NEXT:    seqz a0, a0
18; RV64IZFH-NEXT:    ret
19  %1 = fcmp uno half %a, 0.000000e+00
20  ret i1 %1
21}
22
23define zeroext i1 @half_not_nan(half %a) nounwind {
24; RV32IZFH-LABEL: half_not_nan:
25; RV32IZFH:       # %bb.0:
26; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
27; RV32IZFH-NEXT:    ret
28;
29; RV64IZFH-LABEL: half_not_nan:
30; RV64IZFH:       # %bb.0:
31; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
32; RV64IZFH-NEXT:    ret
33  %1 = fcmp ord half %a, 0.000000e+00
34  ret i1 %1
35}
36