1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s 4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ 5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s 6 7; TODO: the quality of the generated code is poor 8 9define void @test() { 10; RV32I-FPELIM-LABEL: test: 11; RV32I-FPELIM: # %bb.0: 12; RV32I-FPELIM-NEXT: lui a0, 74565 13; RV32I-FPELIM-NEXT: addi a0, a0, 1664 14; RV32I-FPELIM-NEXT: sub sp, sp, a0 15; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 305419904 16; RV32I-FPELIM-NEXT: lui a0, 74565 17; RV32I-FPELIM-NEXT: addi a0, a0, 1664 18; RV32I-FPELIM-NEXT: add sp, sp, a0 19; RV32I-FPELIM-NEXT: ret 20; 21; RV32I-WITHFP-LABEL: test: 22; RV32I-WITHFP: # %bb.0: 23; RV32I-WITHFP-NEXT: addi sp, sp, -2032 24; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032 25; RV32I-WITHFP-NEXT: sw ra, 2028(sp) 26; RV32I-WITHFP-NEXT: sw s0, 2024(sp) 27; RV32I-WITHFP-NEXT: .cfi_offset ra, -4 28; RV32I-WITHFP-NEXT: .cfi_offset s0, -8 29; RV32I-WITHFP-NEXT: addi s0, sp, 2032 30; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0 31; RV32I-WITHFP-NEXT: lui a0, 74565 32; RV32I-WITHFP-NEXT: addi a0, a0, -352 33; RV32I-WITHFP-NEXT: sub sp, sp, a0 34; RV32I-WITHFP-NEXT: lui a0, 74565 35; RV32I-WITHFP-NEXT: addi a0, a0, -352 36; RV32I-WITHFP-NEXT: add sp, sp, a0 37; RV32I-WITHFP-NEXT: lw s0, 2024(sp) 38; RV32I-WITHFP-NEXT: lw ra, 2028(sp) 39; RV32I-WITHFP-NEXT: addi sp, sp, 2032 40; RV32I-WITHFP-NEXT: ret 41 %tmp = alloca [ 305419896 x i8 ] , align 4 42 ret void 43} 44 45; This test case artificially produces register pressure which should force 46; use of the emergency spill slot. 47 48define void @test_emergency_spill_slot(i32 %a) { 49; RV32I-FPELIM-LABEL: test_emergency_spill_slot: 50; RV32I-FPELIM: # %bb.0: 51; RV32I-FPELIM-NEXT: addi sp, sp, -2032 52; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032 53; RV32I-FPELIM-NEXT: sw s0, 2028(sp) 54; RV32I-FPELIM-NEXT: sw s1, 2024(sp) 55; RV32I-FPELIM-NEXT: .cfi_offset s0, -4 56; RV32I-FPELIM-NEXT: .cfi_offset s1, -8 57; RV32I-FPELIM-NEXT: lui a1, 97 58; RV32I-FPELIM-NEXT: addi a1, a1, 672 59; RV32I-FPELIM-NEXT: sub sp, sp, a1 60; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 400016 61; RV32I-FPELIM-NEXT: lui a1, 78 62; RV32I-FPELIM-NEXT: addi a1, a1, 512 63; RV32I-FPELIM-NEXT: addi a2, sp, 8 64; RV32I-FPELIM-NEXT: add a1, a2, a1 65; RV32I-FPELIM-NEXT: #APP 66; RV32I-FPELIM-NEXT: nop 67; RV32I-FPELIM-EMPTY: 68; RV32I-FPELIM-NEXT: #NO_APP 69; RV32I-FPELIM-NEXT: sw a0, 0(a1) 70; RV32I-FPELIM-NEXT: #APP 71; RV32I-FPELIM-NEXT: nop 72; RV32I-FPELIM-EMPTY: 73; RV32I-FPELIM-NEXT: #NO_APP 74; RV32I-FPELIM-NEXT: lui a0, 97 75; RV32I-FPELIM-NEXT: addi a0, a0, 672 76; RV32I-FPELIM-NEXT: add sp, sp, a0 77; RV32I-FPELIM-NEXT: lw s1, 2024(sp) 78; RV32I-FPELIM-NEXT: lw s0, 2028(sp) 79; RV32I-FPELIM-NEXT: addi sp, sp, 2032 80; RV32I-FPELIM-NEXT: ret 81; 82; RV32I-WITHFP-LABEL: test_emergency_spill_slot: 83; RV32I-WITHFP: # %bb.0: 84; RV32I-WITHFP-NEXT: addi sp, sp, -2032 85; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032 86; RV32I-WITHFP-NEXT: sw ra, 2028(sp) 87; RV32I-WITHFP-NEXT: sw s0, 2024(sp) 88; RV32I-WITHFP-NEXT: sw s1, 2020(sp) 89; RV32I-WITHFP-NEXT: sw s2, 2016(sp) 90; RV32I-WITHFP-NEXT: .cfi_offset ra, -4 91; RV32I-WITHFP-NEXT: .cfi_offset s0, -8 92; RV32I-WITHFP-NEXT: .cfi_offset s1, -12 93; RV32I-WITHFP-NEXT: .cfi_offset s2, -16 94; RV32I-WITHFP-NEXT: addi s0, sp, 2032 95; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0 96; RV32I-WITHFP-NEXT: lui a1, 97 97; RV32I-WITHFP-NEXT: addi a1, a1, 688 98; RV32I-WITHFP-NEXT: sub sp, sp, a1 99; RV32I-WITHFP-NEXT: lui a1, 78 100; RV32I-WITHFP-NEXT: addi a1, a1, 512 101; RV32I-WITHFP-NEXT: lui a2, 1048478 102; RV32I-WITHFP-NEXT: addi a2, a2, 1388 103; RV32I-WITHFP-NEXT: add a2, s0, a2 104; RV32I-WITHFP-NEXT: mv a2, a2 105; RV32I-WITHFP-NEXT: add a1, a2, a1 106; RV32I-WITHFP-NEXT: #APP 107; RV32I-WITHFP-NEXT: nop 108; RV32I-WITHFP-EMPTY: 109; RV32I-WITHFP-NEXT: #NO_APP 110; RV32I-WITHFP-NEXT: sw a0, 0(a1) 111; RV32I-WITHFP-NEXT: #APP 112; RV32I-WITHFP-NEXT: nop 113; RV32I-WITHFP-EMPTY: 114; RV32I-WITHFP-NEXT: #NO_APP 115; RV32I-WITHFP-NEXT: lui a0, 97 116; RV32I-WITHFP-NEXT: addi a0, a0, 688 117; RV32I-WITHFP-NEXT: add sp, sp, a0 118; RV32I-WITHFP-NEXT: lw s2, 2016(sp) 119; RV32I-WITHFP-NEXT: lw s1, 2020(sp) 120; RV32I-WITHFP-NEXT: lw s0, 2024(sp) 121; RV32I-WITHFP-NEXT: lw ra, 2028(sp) 122; RV32I-WITHFP-NEXT: addi sp, sp, 2032 123; RV32I-WITHFP-NEXT: ret 124 %data = alloca [ 100000 x i32 ] , align 4 125 %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000 126 %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"() 127 %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0 128 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1 129 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2 130 %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3 131 %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4 132 %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5 133 %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6 134 %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7 135 %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8 136 %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9 137 %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10 138 %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11 139 %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12 140 %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13 141 %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14 142 store volatile i32 %a, i32* %ptr 143 tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14) 144 ret void 145} 146