1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32 %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64 %s
6
7define void @test1(float* %a, float* %b) nounwind {
8; RV32-LABEL: test1:
9; RV32:       # %bb.0: # %entry
10; RV32-NEXT:    lw a1, 0(a1)
11; RV32-NEXT:    lui a2, 524288
12; RV32-NEXT:    xor a1, a1, a2
13; RV32-NEXT:    sw a1, 0(a0)
14; RV32-NEXT:    ret
15;
16; RV64-LABEL: test1:
17; RV64:       # %bb.0: # %entry
18; RV64-NEXT:    lw a1, 0(a1)
19; RV64-NEXT:    addi a2, zero, 1
20; RV64-NEXT:    slli a2, a2, 31
21; RV64-NEXT:    xor a1, a1, a2
22; RV64-NEXT:    sw a1, 0(a0)
23; RV64-NEXT:    ret
24entry:
25  %0 = load float, float* %b
26  %neg = fneg float %0
27  store float %neg, float* %a
28  ret void
29}
30
31define void @test2(double* %a, double* %b) nounwind {
32; RV32-LABEL: test2:
33; RV32:       # %bb.0: # %entry
34; RV32-NEXT:    lw a2, 4(a1)
35; RV32-NEXT:    lw a1, 0(a1)
36; RV32-NEXT:    lui a3, 524288
37; RV32-NEXT:    xor a2, a2, a3
38; RV32-NEXT:    sw a1, 0(a0)
39; RV32-NEXT:    sw a2, 4(a0)
40; RV32-NEXT:    ret
41;
42; RV64-LABEL: test2:
43; RV64:       # %bb.0: # %entry
44; RV64-NEXT:    ld a1, 0(a1)
45; RV64-NEXT:    addi a2, zero, -1
46; RV64-NEXT:    slli a2, a2, 63
47; RV64-NEXT:    xor a1, a1, a2
48; RV64-NEXT:    sd a1, 0(a0)
49; RV64-NEXT:    ret
50entry:
51  %0 = load double, double* %b
52  %neg = fneg double %0
53  store double %neg, double* %a
54  ret void
55}
56
57define void @test3(fp128* %a, fp128* %b) nounwind {
58; RV32-LABEL: test3:
59; RV32:       # %bb.0: # %entry
60; RV32-NEXT:    lw a2, 4(a1)
61; RV32-NEXT:    lw a3, 12(a1)
62; RV32-NEXT:    lw a4, 8(a1)
63; RV32-NEXT:    lw a1, 0(a1)
64; RV32-NEXT:    lui a5, 524288
65; RV32-NEXT:    xor a3, a3, a5
66; RV32-NEXT:    sw a4, 8(a0)
67; RV32-NEXT:    sw a1, 0(a0)
68; RV32-NEXT:    sw a2, 4(a0)
69; RV32-NEXT:    sw a3, 12(a0)
70; RV32-NEXT:    ret
71;
72; RV64-LABEL: test3:
73; RV64:       # %bb.0: # %entry
74; RV64-NEXT:    ld a2, 8(a1)
75; RV64-NEXT:    ld a1, 0(a1)
76; RV64-NEXT:    addi a3, zero, -1
77; RV64-NEXT:    slli a3, a3, 63
78; RV64-NEXT:    xor a2, a2, a3
79; RV64-NEXT:    sd a1, 0(a0)
80; RV64-NEXT:    sd a2, 8(a0)
81; RV64-NEXT:    ret
82entry:
83  %0 = load fp128, fp128* %b
84  %neg = fneg fp128 %0
85  store fp128 %neg, fp128* %a
86  ret void
87}
88