1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32-unknown-unknown | FileCheck %s --check-prefix=RV32
3; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown | FileCheck %s --check-prefix=RV64
4
5declare i32 @llvm.abs.i32(i32, i1 immarg)
6declare i64 @llvm.abs.i64(i64, i1 immarg)
7
8define i32 @neg_abs32(i32 %x) {
9; RV32-LABEL: neg_abs32:
10; RV32:       # %bb.0:
11; RV32-NEXT:    srai a1, a0, 31
12; RV32-NEXT:    xor a0, a0, a1
13; RV32-NEXT:    sub a0, a1, a0
14; RV32-NEXT:    ret
15;
16; RV64-LABEL: neg_abs32:
17; RV64:       # %bb.0:
18; RV64-NEXT:    sraiw a1, a0, 31
19; RV64-NEXT:    xor a0, a0, a1
20; RV64-NEXT:    subw a0, a1, a0
21; RV64-NEXT:    ret
22  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
23  %neg = sub nsw i32 0, %abs
24  ret i32 %neg
25}
26
27define i32 @select_neg_abs32(i32 %x) {
28; RV32-LABEL: select_neg_abs32:
29; RV32:       # %bb.0:
30; RV32-NEXT:    srai a1, a0, 31
31; RV32-NEXT:    xor a0, a0, a1
32; RV32-NEXT:    sub a0, a1, a0
33; RV32-NEXT:    ret
34;
35; RV64-LABEL: select_neg_abs32:
36; RV64:       # %bb.0:
37; RV64-NEXT:    sraiw a1, a0, 31
38; RV64-NEXT:    xor a0, a0, a1
39; RV64-NEXT:    subw a0, a1, a0
40; RV64-NEXT:    ret
41  %1 = icmp slt i32 %x, 0
42  %2 = sub nsw i32 0, %x
43  %3 = select i1 %1, i32 %x, i32 %2
44  ret i32 %3
45}
46
47define i64 @neg_abs64(i64 %x) {
48; RV32-LABEL: neg_abs64:
49; RV32:       # %bb.0:
50; RV32-NEXT:    srai a2, a1, 31
51; RV32-NEXT:    xor a0, a0, a2
52; RV32-NEXT:    sltu a3, a2, a0
53; RV32-NEXT:    xor a1, a1, a2
54; RV32-NEXT:    sub a1, a2, a1
55; RV32-NEXT:    sub a1, a1, a3
56; RV32-NEXT:    sub a0, a2, a0
57; RV32-NEXT:    ret
58;
59; RV64-LABEL: neg_abs64:
60; RV64:       # %bb.0:
61; RV64-NEXT:    srai a1, a0, 63
62; RV64-NEXT:    xor a0, a0, a1
63; RV64-NEXT:    sub a0, a1, a0
64; RV64-NEXT:    ret
65  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
66  %neg = sub nsw i64 0, %abs
67  ret i64 %neg
68}
69
70define i64 @select_neg_abs64(i64 %x) {
71; RV32-LABEL: select_neg_abs64:
72; RV32:       # %bb.0:
73; RV32-NEXT:    srai a2, a1, 31
74; RV32-NEXT:    xor a0, a0, a2
75; RV32-NEXT:    sltu a3, a2, a0
76; RV32-NEXT:    xor a1, a1, a2
77; RV32-NEXT:    sub a1, a2, a1
78; RV32-NEXT:    sub a1, a1, a3
79; RV32-NEXT:    sub a0, a2, a0
80; RV32-NEXT:    ret
81;
82; RV64-LABEL: select_neg_abs64:
83; RV64:       # %bb.0:
84; RV64-NEXT:    srai a1, a0, 63
85; RV64-NEXT:    xor a0, a0, a1
86; RV64-NEXT:    sub a0, a1, a0
87; RV64-NEXT:    ret
88  %1 = icmp slt i64 %x, 0
89  %2 = sub nsw i64 0, %x
90  %3 = select i1 %1, i64 %x, i64 %2
91  ret i64 %3
92}
93
94