1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV32IM %s 6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 7; RUN: | FileCheck -check-prefix=RV64I %s 8; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ 9; RUN: | FileCheck -check-prefix=RV64IM %s 10 11define i32 @urem(i32 %a, i32 %b) nounwind { 12; RV32I-LABEL: urem: 13; RV32I: # %bb.0: 14; RV32I-NEXT: addi sp, sp, -16 15; RV32I-NEXT: sw ra, 12(sp) 16; RV32I-NEXT: call __umodsi3 17; RV32I-NEXT: lw ra, 12(sp) 18; RV32I-NEXT: addi sp, sp, 16 19; RV32I-NEXT: ret 20; 21; RV32IM-LABEL: urem: 22; RV32IM: # %bb.0: 23; RV32IM-NEXT: remu a0, a0, a1 24; RV32IM-NEXT: ret 25; 26; RV64I-LABEL: urem: 27; RV64I: # %bb.0: 28; RV64I-NEXT: addi sp, sp, -16 29; RV64I-NEXT: sd ra, 8(sp) 30; RV64I-NEXT: slli a0, a0, 32 31; RV64I-NEXT: srli a0, a0, 32 32; RV64I-NEXT: slli a1, a1, 32 33; RV64I-NEXT: srli a1, a1, 32 34; RV64I-NEXT: call __umoddi3 35; RV64I-NEXT: ld ra, 8(sp) 36; RV64I-NEXT: addi sp, sp, 16 37; RV64I-NEXT: ret 38; 39; RV64IM-LABEL: urem: 40; RV64IM: # %bb.0: 41; RV64IM-NEXT: remuw a0, a0, a1 42; RV64IM-NEXT: ret 43 %1 = urem i32 %a, %b 44 ret i32 %1 45} 46 47define i32 @srem(i32 %a, i32 %b) nounwind { 48; RV32I-LABEL: srem: 49; RV32I: # %bb.0: 50; RV32I-NEXT: addi sp, sp, -16 51; RV32I-NEXT: sw ra, 12(sp) 52; RV32I-NEXT: call __modsi3 53; RV32I-NEXT: lw ra, 12(sp) 54; RV32I-NEXT: addi sp, sp, 16 55; RV32I-NEXT: ret 56; 57; RV32IM-LABEL: srem: 58; RV32IM: # %bb.0: 59; RV32IM-NEXT: rem a0, a0, a1 60; RV32IM-NEXT: ret 61; 62; RV64I-LABEL: srem: 63; RV64I: # %bb.0: 64; RV64I-NEXT: addi sp, sp, -16 65; RV64I-NEXT: sd ra, 8(sp) 66; RV64I-NEXT: sext.w a0, a0 67; RV64I-NEXT: sext.w a1, a1 68; RV64I-NEXT: call __moddi3 69; RV64I-NEXT: ld ra, 8(sp) 70; RV64I-NEXT: addi sp, sp, 16 71; RV64I-NEXT: ret 72; 73; RV64IM-LABEL: srem: 74; RV64IM: # %bb.0: 75; RV64IM-NEXT: remw a0, a0, a1 76; RV64IM-NEXT: ret 77 %1 = srem i32 %a, %b 78 ret i32 %1 79} 80