1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4 5; These IR sequences will generate ISD::ROTL and ISD::ROTR nodes, that the 6; RISC-V backend must be able to select 7 8define i32 @rotl(i32 %x, i32 %y) nounwind { 9; RV32I-LABEL: rotl: 10; RV32I: # %bb.0: 11; RV32I-NEXT: addi a2, zero, 32 12; RV32I-NEXT: sub a2, a2, a1 13; RV32I-NEXT: sll a1, a0, a1 14; RV32I-NEXT: srl a0, a0, a2 15; RV32I-NEXT: or a0, a1, a0 16; RV32I-NEXT: ret 17 %z = sub i32 32, %y 18 %b = shl i32 %x, %y 19 %c = lshr i32 %x, %z 20 %d = or i32 %b, %c 21 ret i32 %d 22} 23 24define i32 @rotr(i32 %x, i32 %y) nounwind { 25; RV32I-LABEL: rotr: 26; RV32I: # %bb.0: 27; RV32I-NEXT: addi a2, zero, 32 28; RV32I-NEXT: sub a2, a2, a1 29; RV32I-NEXT: srl a1, a0, a1 30; RV32I-NEXT: sll a0, a0, a2 31; RV32I-NEXT: or a0, a1, a0 32; RV32I-NEXT: ret 33 %z = sub i32 32, %y 34 %b = lshr i32 %x, %y 35 %c = shl i32 %x, %z 36 %d = or i32 %b, %c 37 ret i32 %d 38} 39