1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV32IB
6; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
7; RUN:   | FileCheck %s -check-prefix=RV32IBT
8
9define i32 @cmix_i32(i32 %a, i32 %b, i32 %c) nounwind {
10; RV32I-LABEL: cmix_i32:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    and a0, a1, a0
13; RV32I-NEXT:    not a1, a1
14; RV32I-NEXT:    and a1, a1, a2
15; RV32I-NEXT:    or a0, a1, a0
16; RV32I-NEXT:    ret
17;
18; RV32IB-LABEL: cmix_i32:
19; RV32IB:       # %bb.0:
20; RV32IB-NEXT:    cmix a0, a1, a0, a2
21; RV32IB-NEXT:    ret
22;
23; RV32IBT-LABEL: cmix_i32:
24; RV32IBT:       # %bb.0:
25; RV32IBT-NEXT:    cmix a0, a1, a0, a2
26; RV32IBT-NEXT:    ret
27  %and = and i32 %b, %a
28  %neg = xor i32 %b, -1
29  %and1 = and i32 %neg, %c
30  %or = or i32 %and1, %and
31  ret i32 %or
32}
33
34define i64 @cmix_i64(i64 %a, i64 %b, i64 %c) nounwind {
35; RV32I-LABEL: cmix_i64:
36; RV32I:       # %bb.0:
37; RV32I-NEXT:    and a1, a3, a1
38; RV32I-NEXT:    and a0, a2, a0
39; RV32I-NEXT:    not a2, a2
40; RV32I-NEXT:    not a3, a3
41; RV32I-NEXT:    and a3, a3, a5
42; RV32I-NEXT:    and a2, a2, a4
43; RV32I-NEXT:    or a0, a2, a0
44; RV32I-NEXT:    or a1, a3, a1
45; RV32I-NEXT:    ret
46;
47; RV32IB-LABEL: cmix_i64:
48; RV32IB:       # %bb.0:
49; RV32IB-NEXT:    cmix a0, a2, a0, a4
50; RV32IB-NEXT:    cmix a1, a3, a1, a5
51; RV32IB-NEXT:    ret
52;
53; RV32IBT-LABEL: cmix_i64:
54; RV32IBT:       # %bb.0:
55; RV32IBT-NEXT:    cmix a0, a2, a0, a4
56; RV32IBT-NEXT:    cmix a1, a3, a1, a5
57; RV32IBT-NEXT:    ret
58  %and = and i64 %b, %a
59  %neg = xor i64 %b, -1
60  %and1 = and i64 %neg, %c
61  %or = or i64 %and1, %and
62  ret i64 %or
63}
64
65define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
66; RV32I-LABEL: cmov_i32:
67; RV32I:       # %bb.0:
68; RV32I-NEXT:    beqz a1, .LBB2_2
69; RV32I-NEXT:  # %bb.1:
70; RV32I-NEXT:    mv a2, a0
71; RV32I-NEXT:  .LBB2_2:
72; RV32I-NEXT:    mv a0, a2
73; RV32I-NEXT:    ret
74;
75; RV32IB-LABEL: cmov_i32:
76; RV32IB:       # %bb.0:
77; RV32IB-NEXT:    cmov a0, a1, a0, a2
78; RV32IB-NEXT:    ret
79;
80; RV32IBT-LABEL: cmov_i32:
81; RV32IBT:       # %bb.0:
82; RV32IBT-NEXT:    cmov a0, a1, a0, a2
83; RV32IBT-NEXT:    ret
84  %tobool.not = icmp eq i32 %b, 0
85  %cond = select i1 %tobool.not, i32 %c, i32 %a
86  ret i32 %cond
87}
88
89define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
90; RV32I-LABEL: cmov_i64:
91; RV32I:       # %bb.0:
92; RV32I-NEXT:    or a2, a2, a3
93; RV32I-NEXT:    beqz a2, .LBB3_2
94; RV32I-NEXT:  # %bb.1:
95; RV32I-NEXT:    mv a4, a0
96; RV32I-NEXT:    mv a5, a1
97; RV32I-NEXT:  .LBB3_2:
98; RV32I-NEXT:    mv a0, a4
99; RV32I-NEXT:    mv a1, a5
100; RV32I-NEXT:    ret
101;
102; RV32IB-LABEL: cmov_i64:
103; RV32IB:       # %bb.0:
104; RV32IB-NEXT:    or a2, a2, a3
105; RV32IB-NEXT:    cmov a0, a2, a0, a4
106; RV32IB-NEXT:    cmov a1, a2, a1, a5
107; RV32IB-NEXT:    ret
108;
109; RV32IBT-LABEL: cmov_i64:
110; RV32IBT:       # %bb.0:
111; RV32IBT-NEXT:    or a2, a2, a3
112; RV32IBT-NEXT:    cmov a0, a2, a0, a4
113; RV32IBT-NEXT:    cmov a1, a2, a1, a5
114; RV32IBT-NEXT:    ret
115  %tobool.not = icmp eq i64 %b, 0
116  %cond = select i1 %tobool.not, i64 %c, i64 %a
117  ret i64 %cond
118}
119
120declare i32 @llvm.fshl.i32(i32, i32, i32)
121
122define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
123; RV32I-LABEL: fshl_i32:
124; RV32I:       # %bb.0:
125; RV32I-NEXT:    sll a0, a0, a2
126; RV32I-NEXT:    not a2, a2
127; RV32I-NEXT:    srli a1, a1, 1
128; RV32I-NEXT:    srl a1, a1, a2
129; RV32I-NEXT:    or a0, a0, a1
130; RV32I-NEXT:    ret
131;
132; RV32IB-LABEL: fshl_i32:
133; RV32IB:       # %bb.0:
134; RV32IB-NEXT:    andi a2, a2, 31
135; RV32IB-NEXT:    fsl a0, a0, a1, a2
136; RV32IB-NEXT:    ret
137;
138; RV32IBT-LABEL: fshl_i32:
139; RV32IBT:       # %bb.0:
140; RV32IBT-NEXT:    andi a2, a2, 31
141; RV32IBT-NEXT:    fsl a0, a0, a1, a2
142; RV32IBT-NEXT:    ret
143  %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
144  ret i32 %1
145}
146
147; As we are not matching directly i64 code patterns on RV32 some i64 patterns
148; don't have yet an efficient pattern-matching with bit manipulation
149; instructions on RV32.
150; This test is presented here in case future expansions of the experimental-b
151; extension introduce instructions that can match more efficiently this pattern.
152
153declare i64 @llvm.fshl.i64(i64, i64, i64)
154
155define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
156; RV32I-LABEL: fshl_i64:
157; RV32I:       # %bb.0:
158; RV32I-NEXT:    andi a5, a4, 63
159; RV32I-NEXT:    addi t1, a5, -32
160; RV32I-NEXT:    addi a6, zero, 31
161; RV32I-NEXT:    bltz t1, .LBB5_2
162; RV32I-NEXT:  # %bb.1:
163; RV32I-NEXT:    sll a7, a0, t1
164; RV32I-NEXT:    j .LBB5_3
165; RV32I-NEXT:  .LBB5_2:
166; RV32I-NEXT:    sll a7, a1, a4
167; RV32I-NEXT:    sub a5, a6, a5
168; RV32I-NEXT:    srli a1, a0, 1
169; RV32I-NEXT:    srl a1, a1, a5
170; RV32I-NEXT:    or a7, a7, a1
171; RV32I-NEXT:  .LBB5_3:
172; RV32I-NEXT:    not a1, a4
173; RV32I-NEXT:    andi t3, a1, 63
174; RV32I-NEXT:    addi a5, t3, -32
175; RV32I-NEXT:    srli t2, a3, 1
176; RV32I-NEXT:    bltz a5, .LBB5_7
177; RV32I-NEXT:  # %bb.4:
178; RV32I-NEXT:    mv t0, zero
179; RV32I-NEXT:    bgez a5, .LBB5_8
180; RV32I-NEXT:  .LBB5_5:
181; RV32I-NEXT:    slli a3, a3, 31
182; RV32I-NEXT:    srli a2, a2, 1
183; RV32I-NEXT:    or a2, a2, a3
184; RV32I-NEXT:    srl a1, a2, a1
185; RV32I-NEXT:    sub a2, a6, t3
186; RV32I-NEXT:    slli a3, t2, 1
187; RV32I-NEXT:    sll a2, a3, a2
188; RV32I-NEXT:    or a2, a1, a2
189; RV32I-NEXT:    or a1, a7, t0
190; RV32I-NEXT:    bgez t1, .LBB5_9
191; RV32I-NEXT:  .LBB5_6:
192; RV32I-NEXT:    sll a0, a0, a4
193; RV32I-NEXT:    or a0, a0, a2
194; RV32I-NEXT:    ret
195; RV32I-NEXT:  .LBB5_7:
196; RV32I-NEXT:    srl t0, t2, a1
197; RV32I-NEXT:    bltz a5, .LBB5_5
198; RV32I-NEXT:  .LBB5_8:
199; RV32I-NEXT:    srl a2, t2, a5
200; RV32I-NEXT:    or a1, a7, t0
201; RV32I-NEXT:    bltz t1, .LBB5_6
202; RV32I-NEXT:  .LBB5_9:
203; RV32I-NEXT:    or a0, zero, a2
204; RV32I-NEXT:    ret
205;
206; RV32IB-LABEL: fshl_i64:
207; RV32IB:       # %bb.0:
208; RV32IB-NEXT:    andi a5, a4, 63
209; RV32IB-NEXT:    addi t2, a5, -32
210; RV32IB-NEXT:    addi a6, zero, 31
211; RV32IB-NEXT:    bltz t2, .LBB5_2
212; RV32IB-NEXT:  # %bb.1:
213; RV32IB-NEXT:    sll a7, a0, t2
214; RV32IB-NEXT:    j .LBB5_3
215; RV32IB-NEXT:  .LBB5_2:
216; RV32IB-NEXT:    sll a7, a1, a4
217; RV32IB-NEXT:    sub a5, a6, a5
218; RV32IB-NEXT:    srli a1, a0, 1
219; RV32IB-NEXT:    srl a1, a1, a5
220; RV32IB-NEXT:    or a7, a7, a1
221; RV32IB-NEXT:  .LBB5_3:
222; RV32IB-NEXT:    not t1, a4
223; RV32IB-NEXT:    addi a1, zero, 63
224; RV32IB-NEXT:    andn a5, a1, a4
225; RV32IB-NEXT:    addi a1, a5, -32
226; RV32IB-NEXT:    srli t3, a3, 1
227; RV32IB-NEXT:    bltz a1, .LBB5_7
228; RV32IB-NEXT:  # %bb.4:
229; RV32IB-NEXT:    mv t0, zero
230; RV32IB-NEXT:    bgez a1, .LBB5_8
231; RV32IB-NEXT:  .LBB5_5:
232; RV32IB-NEXT:    fsri a1, a2, a3, 1
233; RV32IB-NEXT:    srl a1, a1, t1
234; RV32IB-NEXT:    sub a2, a6, a5
235; RV32IB-NEXT:    slli a3, t3, 1
236; RV32IB-NEXT:    sll a2, a3, a2
237; RV32IB-NEXT:    or a2, a1, a2
238; RV32IB-NEXT:    or a1, a7, t0
239; RV32IB-NEXT:    bgez t2, .LBB5_9
240; RV32IB-NEXT:  .LBB5_6:
241; RV32IB-NEXT:    sll a0, a0, a4
242; RV32IB-NEXT:    or a0, a0, a2
243; RV32IB-NEXT:    ret
244; RV32IB-NEXT:  .LBB5_7:
245; RV32IB-NEXT:    srl t0, t3, t1
246; RV32IB-NEXT:    bltz a1, .LBB5_5
247; RV32IB-NEXT:  .LBB5_8:
248; RV32IB-NEXT:    srl a2, t3, a1
249; RV32IB-NEXT:    or a1, a7, t0
250; RV32IB-NEXT:    bltz t2, .LBB5_6
251; RV32IB-NEXT:  .LBB5_9:
252; RV32IB-NEXT:    or a0, zero, a2
253; RV32IB-NEXT:    ret
254;
255; RV32IBT-LABEL: fshl_i64:
256; RV32IBT:       # %bb.0:
257; RV32IBT-NEXT:    andi a5, a4, 63
258; RV32IBT-NEXT:    addi t1, a5, -32
259; RV32IBT-NEXT:    addi a6, zero, 31
260; RV32IBT-NEXT:    bltz t1, .LBB5_2
261; RV32IBT-NEXT:  # %bb.1:
262; RV32IBT-NEXT:    sll a7, a0, t1
263; RV32IBT-NEXT:    j .LBB5_3
264; RV32IBT-NEXT:  .LBB5_2:
265; RV32IBT-NEXT:    sll a7, a1, a4
266; RV32IBT-NEXT:    sub a5, a6, a5
267; RV32IBT-NEXT:    srli a1, a0, 1
268; RV32IBT-NEXT:    srl a1, a1, a5
269; RV32IBT-NEXT:    or a7, a7, a1
270; RV32IBT-NEXT:  .LBB5_3:
271; RV32IBT-NEXT:    not a1, a4
272; RV32IBT-NEXT:    andi t3, a1, 63
273; RV32IBT-NEXT:    addi a5, t3, -32
274; RV32IBT-NEXT:    srli t2, a3, 1
275; RV32IBT-NEXT:    bltz a5, .LBB5_7
276; RV32IBT-NEXT:  # %bb.4:
277; RV32IBT-NEXT:    mv t0, zero
278; RV32IBT-NEXT:    bgez a5, .LBB5_8
279; RV32IBT-NEXT:  .LBB5_5:
280; RV32IBT-NEXT:    fsri a2, a2, a3, 1
281; RV32IBT-NEXT:    srl a1, a2, a1
282; RV32IBT-NEXT:    sub a2, a6, t3
283; RV32IBT-NEXT:    slli a3, t2, 1
284; RV32IBT-NEXT:    sll a2, a3, a2
285; RV32IBT-NEXT:    or a2, a1, a2
286; RV32IBT-NEXT:    or a1, a7, t0
287; RV32IBT-NEXT:    bgez t1, .LBB5_9
288; RV32IBT-NEXT:  .LBB5_6:
289; RV32IBT-NEXT:    sll a0, a0, a4
290; RV32IBT-NEXT:    or a0, a0, a2
291; RV32IBT-NEXT:    ret
292; RV32IBT-NEXT:  .LBB5_7:
293; RV32IBT-NEXT:    srl t0, t2, a1
294; RV32IBT-NEXT:    bltz a5, .LBB5_5
295; RV32IBT-NEXT:  .LBB5_8:
296; RV32IBT-NEXT:    srl a2, t2, a5
297; RV32IBT-NEXT:    or a1, a7, t0
298; RV32IBT-NEXT:    bltz t1, .LBB5_6
299; RV32IBT-NEXT:  .LBB5_9:
300; RV32IBT-NEXT:    or a0, zero, a2
301; RV32IBT-NEXT:    ret
302  %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
303  ret i64 %1
304}
305
306declare i32 @llvm.fshr.i32(i32, i32, i32)
307
308define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) nounwind {
309; RV32I-LABEL: fshr_i32:
310; RV32I:       # %bb.0:
311; RV32I-NEXT:    srl a1, a1, a2
312; RV32I-NEXT:    not a2, a2
313; RV32I-NEXT:    slli a0, a0, 1
314; RV32I-NEXT:    sll a0, a0, a2
315; RV32I-NEXT:    or a0, a0, a1
316; RV32I-NEXT:    ret
317;
318; RV32IB-LABEL: fshr_i32:
319; RV32IB:       # %bb.0:
320; RV32IB-NEXT:    andi a2, a2, 31
321; RV32IB-NEXT:    fsr a0, a1, a0, a2
322; RV32IB-NEXT:    ret
323;
324; RV32IBT-LABEL: fshr_i32:
325; RV32IBT:       # %bb.0:
326; RV32IBT-NEXT:    andi a2, a2, 31
327; RV32IBT-NEXT:    fsr a0, a1, a0, a2
328; RV32IBT-NEXT:    ret
329  %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
330  ret i32 %1
331}
332
333; As we are not matching directly i64 code patterns on RV32 some i64 patterns
334; don't have yet an efficient pattern-matching with bit manipulation
335; instructions on RV32.
336; This test is presented here in case future expansions of the experimental-b
337; extension introduce instructions that can match more efficiently this pattern.
338
339declare i64 @llvm.fshr.i64(i64, i64, i64)
340
341define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
342; RV32I-LABEL: fshr_i64:
343; RV32I:       # %bb.0:
344; RV32I-NEXT:    andi a5, a4, 63
345; RV32I-NEXT:    addi t1, a5, -32
346; RV32I-NEXT:    addi a6, zero, 31
347; RV32I-NEXT:    bltz t1, .LBB7_2
348; RV32I-NEXT:  # %bb.1:
349; RV32I-NEXT:    srl a7, a3, t1
350; RV32I-NEXT:    j .LBB7_3
351; RV32I-NEXT:  .LBB7_2:
352; RV32I-NEXT:    srl a7, a2, a4
353; RV32I-NEXT:    sub a5, a6, a5
354; RV32I-NEXT:    slli a2, a3, 1
355; RV32I-NEXT:    sll a2, a2, a5
356; RV32I-NEXT:    or a7, a7, a2
357; RV32I-NEXT:  .LBB7_3:
358; RV32I-NEXT:    not a2, a4
359; RV32I-NEXT:    andi t2, a2, 63
360; RV32I-NEXT:    addi a5, t2, -32
361; RV32I-NEXT:    slli t3, a0, 1
362; RV32I-NEXT:    bltz a5, .LBB7_7
363; RV32I-NEXT:  # %bb.4:
364; RV32I-NEXT:    mv t0, zero
365; RV32I-NEXT:    bgez a5, .LBB7_8
366; RV32I-NEXT:  .LBB7_5:
367; RV32I-NEXT:    lui a5, 524288
368; RV32I-NEXT:    addi a5, a5, -1
369; RV32I-NEXT:    and t3, a0, a5
370; RV32I-NEXT:    sub a5, a6, t2
371; RV32I-NEXT:    srl a5, t3, a5
372; RV32I-NEXT:    srli a0, a0, 31
373; RV32I-NEXT:    slli a1, a1, 1
374; RV32I-NEXT:    or a0, a1, a0
375; RV32I-NEXT:    sll a0, a0, a2
376; RV32I-NEXT:    or a1, a0, a5
377; RV32I-NEXT:    or a0, t0, a7
378; RV32I-NEXT:    bgez t1, .LBB7_9
379; RV32I-NEXT:  .LBB7_6:
380; RV32I-NEXT:    srl a2, a3, a4
381; RV32I-NEXT:    or a1, a1, a2
382; RV32I-NEXT:    ret
383; RV32I-NEXT:  .LBB7_7:
384; RV32I-NEXT:    sll t0, t3, a2
385; RV32I-NEXT:    bltz a5, .LBB7_5
386; RV32I-NEXT:  .LBB7_8:
387; RV32I-NEXT:    sll a1, t3, a5
388; RV32I-NEXT:    or a0, t0, a7
389; RV32I-NEXT:    bltz t1, .LBB7_6
390; RV32I-NEXT:  .LBB7_9:
391; RV32I-NEXT:    or a1, a1, zero
392; RV32I-NEXT:    ret
393;
394; RV32IB-LABEL: fshr_i64:
395; RV32IB:       # %bb.0:
396; RV32IB-NEXT:    andi a5, a4, 63
397; RV32IB-NEXT:    addi t2, a5, -32
398; RV32IB-NEXT:    addi a6, zero, 31
399; RV32IB-NEXT:    bltz t2, .LBB7_2
400; RV32IB-NEXT:  # %bb.1:
401; RV32IB-NEXT:    srl a7, a3, t2
402; RV32IB-NEXT:    j .LBB7_3
403; RV32IB-NEXT:  .LBB7_2:
404; RV32IB-NEXT:    srl a7, a2, a4
405; RV32IB-NEXT:    sub a5, a6, a5
406; RV32IB-NEXT:    slli a2, a3, 1
407; RV32IB-NEXT:    sll a2, a2, a5
408; RV32IB-NEXT:    or a7, a7, a2
409; RV32IB-NEXT:  .LBB7_3:
410; RV32IB-NEXT:    not t1, a4
411; RV32IB-NEXT:    addi a2, zero, 63
412; RV32IB-NEXT:    andn a2, a2, a4
413; RV32IB-NEXT:    addi a5, a2, -32
414; RV32IB-NEXT:    slli t3, a0, 1
415; RV32IB-NEXT:    bltz a5, .LBB7_7
416; RV32IB-NEXT:  # %bb.4:
417; RV32IB-NEXT:    mv t0, zero
418; RV32IB-NEXT:    bgez a5, .LBB7_8
419; RV32IB-NEXT:  .LBB7_5:
420; RV32IB-NEXT:    fsri a1, a0, a1, 31
421; RV32IB-NEXT:    sll a1, a1, t1
422; RV32IB-NEXT:    sub a2, a6, a2
423; RV32IB-NEXT:    sbclri a0, a0, 31
424; RV32IB-NEXT:    srl a0, a0, a2
425; RV32IB-NEXT:    or a1, a1, a0
426; RV32IB-NEXT:    or a0, t0, a7
427; RV32IB-NEXT:    bgez t2, .LBB7_9
428; RV32IB-NEXT:  .LBB7_6:
429; RV32IB-NEXT:    srl a2, a3, a4
430; RV32IB-NEXT:    or a1, a1, a2
431; RV32IB-NEXT:    ret
432; RV32IB-NEXT:  .LBB7_7:
433; RV32IB-NEXT:    sll t0, t3, t1
434; RV32IB-NEXT:    bltz a5, .LBB7_5
435; RV32IB-NEXT:  .LBB7_8:
436; RV32IB-NEXT:    sll a1, t3, a5
437; RV32IB-NEXT:    or a0, t0, a7
438; RV32IB-NEXT:    bltz t2, .LBB7_6
439; RV32IB-NEXT:  .LBB7_9:
440; RV32IB-NEXT:    or a1, a1, zero
441; RV32IB-NEXT:    ret
442;
443; RV32IBT-LABEL: fshr_i64:
444; RV32IBT:       # %bb.0:
445; RV32IBT-NEXT:    andi a5, a4, 63
446; RV32IBT-NEXT:    addi t1, a5, -32
447; RV32IBT-NEXT:    addi a6, zero, 31
448; RV32IBT-NEXT:    bltz t1, .LBB7_2
449; RV32IBT-NEXT:  # %bb.1:
450; RV32IBT-NEXT:    srl a7, a3, t1
451; RV32IBT-NEXT:    j .LBB7_3
452; RV32IBT-NEXT:  .LBB7_2:
453; RV32IBT-NEXT:    srl a7, a2, a4
454; RV32IBT-NEXT:    sub a5, a6, a5
455; RV32IBT-NEXT:    slli a2, a3, 1
456; RV32IBT-NEXT:    sll a2, a2, a5
457; RV32IBT-NEXT:    or a7, a7, a2
458; RV32IBT-NEXT:  .LBB7_3:
459; RV32IBT-NEXT:    not a2, a4
460; RV32IBT-NEXT:    andi t2, a2, 63
461; RV32IBT-NEXT:    addi a5, t2, -32
462; RV32IBT-NEXT:    slli t3, a0, 1
463; RV32IBT-NEXT:    bltz a5, .LBB7_7
464; RV32IBT-NEXT:  # %bb.4:
465; RV32IBT-NEXT:    mv t0, zero
466; RV32IBT-NEXT:    bgez a5, .LBB7_8
467; RV32IBT-NEXT:  .LBB7_5:
468; RV32IBT-NEXT:    lui a5, 524288
469; RV32IBT-NEXT:    addi a5, a5, -1
470; RV32IBT-NEXT:    and t3, a0, a5
471; RV32IBT-NEXT:    sub a5, a6, t2
472; RV32IBT-NEXT:    srl a5, t3, a5
473; RV32IBT-NEXT:    fsri a0, a0, a1, 31
474; RV32IBT-NEXT:    sll a0, a0, a2
475; RV32IBT-NEXT:    or a1, a0, a5
476; RV32IBT-NEXT:    or a0, t0, a7
477; RV32IBT-NEXT:    bgez t1, .LBB7_9
478; RV32IBT-NEXT:  .LBB7_6:
479; RV32IBT-NEXT:    srl a2, a3, a4
480; RV32IBT-NEXT:    or a1, a1, a2
481; RV32IBT-NEXT:    ret
482; RV32IBT-NEXT:  .LBB7_7:
483; RV32IBT-NEXT:    sll t0, t3, a2
484; RV32IBT-NEXT:    bltz a5, .LBB7_5
485; RV32IBT-NEXT:  .LBB7_8:
486; RV32IBT-NEXT:    sll a1, t3, a5
487; RV32IBT-NEXT:    or a0, t0, a7
488; RV32IBT-NEXT:    bltz t1, .LBB7_6
489; RV32IBT-NEXT:  .LBB7_9:
490; RV32IBT-NEXT:    or a1, a1, zero
491; RV32IBT-NEXT:    ret
492  %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
493  ret i64 %1
494}
495
496define i32 @fshri_i32(i32 %a, i32 %b) nounwind {
497; RV32I-LABEL: fshri_i32:
498; RV32I:       # %bb.0:
499; RV32I-NEXT:    srli a1, a1, 5
500; RV32I-NEXT:    slli a0, a0, 27
501; RV32I-NEXT:    or a0, a0, a1
502; RV32I-NEXT:    ret
503;
504; RV32IB-LABEL: fshri_i32:
505; RV32IB:       # %bb.0:
506; RV32IB-NEXT:    fsri a0, a1, a0, 5
507; RV32IB-NEXT:    ret
508;
509; RV32IBT-LABEL: fshri_i32:
510; RV32IBT:       # %bb.0:
511; RV32IBT-NEXT:    fsri a0, a1, a0, 5
512; RV32IBT-NEXT:    ret
513  %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
514  ret i32 %1
515}
516
517define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
518; RV32I-LABEL: fshri_i64:
519; RV32I:       # %bb.0:
520; RV32I-NEXT:    slli a1, a3, 27
521; RV32I-NEXT:    srli a2, a2, 5
522; RV32I-NEXT:    or a2, a2, a1
523; RV32I-NEXT:    srli a1, a3, 5
524; RV32I-NEXT:    slli a0, a0, 27
525; RV32I-NEXT:    or a1, a0, a1
526; RV32I-NEXT:    mv a0, a2
527; RV32I-NEXT:    ret
528;
529; RV32IB-LABEL: fshri_i64:
530; RV32IB:       # %bb.0:
531; RV32IB-NEXT:    fsri a2, a2, a3, 5
532; RV32IB-NEXT:    fsri a1, a3, a0, 5
533; RV32IB-NEXT:    mv a0, a2
534; RV32IB-NEXT:    ret
535;
536; RV32IBT-LABEL: fshri_i64:
537; RV32IBT:       # %bb.0:
538; RV32IBT-NEXT:    fsri a2, a2, a3, 5
539; RV32IBT-NEXT:    fsri a1, a3, a0, 5
540; RV32IBT-NEXT:    mv a0, a2
541; RV32IBT-NEXT:    ret
542  %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
543  ret i64 %1
544}
545
546define i32 @fshli_i32(i32 %a, i32 %b) nounwind {
547; RV32I-LABEL: fshli_i32:
548; RV32I:       # %bb.0:
549; RV32I-NEXT:    srli a1, a1, 27
550; RV32I-NEXT:    slli a0, a0, 5
551; RV32I-NEXT:    or a0, a0, a1
552; RV32I-NEXT:    ret
553;
554; RV32IB-LABEL: fshli_i32:
555; RV32IB:       # %bb.0:
556; RV32IB-NEXT:    fsri a0, a1, a0, 27
557; RV32IB-NEXT:    ret
558;
559; RV32IBT-LABEL: fshli_i32:
560; RV32IBT:       # %bb.0:
561; RV32IBT-NEXT:    fsri a0, a1, a0, 27
562; RV32IBT-NEXT:    ret
563  %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
564  ret i32 %1
565}
566
567define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
568; RV32I-LABEL: fshli_i64:
569; RV32I:       # %bb.0:
570; RV32I-NEXT:    srli a2, a3, 27
571; RV32I-NEXT:    slli a3, a0, 5
572; RV32I-NEXT:    or a2, a3, a2
573; RV32I-NEXT:    srli a0, a0, 27
574; RV32I-NEXT:    slli a1, a1, 5
575; RV32I-NEXT:    or a1, a1, a0
576; RV32I-NEXT:    mv a0, a2
577; RV32I-NEXT:    ret
578;
579; RV32IB-LABEL: fshli_i64:
580; RV32IB:       # %bb.0:
581; RV32IB-NEXT:    fsri a2, a3, a0, 27
582; RV32IB-NEXT:    fsri a1, a0, a1, 27
583; RV32IB-NEXT:    mv a0, a2
584; RV32IB-NEXT:    ret
585;
586; RV32IBT-LABEL: fshli_i64:
587; RV32IBT:       # %bb.0:
588; RV32IBT-NEXT:    fsri a2, a3, a0, 27
589; RV32IBT-NEXT:    fsri a1, a0, a1, 27
590; RV32IBT-NEXT:    mv a0, a2
591; RV32IBT-NEXT:    ret
592  %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
593  ret i64 %1
594}
595