1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7; This file provides a simple sanity check of float and double operations for
8; RV32I and RV64I. This is primarily intended to ensure that custom
9; legalisation or DAG combines aren't incorrectly triggered when the F
10; extension isn't enabled.
11
12; TODO: f32 parameters on RV64 with a soft-float ABI are anyext.
13
14define float @float_test(float %a, float %b) nounwind {
15; RV32IF-LABEL: float_test:
16; RV32IF:       # %bb.0:
17; RV32IF-NEXT:    addi sp, sp, -16
18; RV32IF-NEXT:    sw ra, 12(sp)
19; RV32IF-NEXT:    sw s0, 8(sp)
20; RV32IF-NEXT:    mv s0, a1
21; RV32IF-NEXT:    call __addsf3
22; RV32IF-NEXT:    mv a1, s0
23; RV32IF-NEXT:    call __divsf3
24; RV32IF-NEXT:    lw s0, 8(sp)
25; RV32IF-NEXT:    lw ra, 12(sp)
26; RV32IF-NEXT:    addi sp, sp, 16
27; RV32IF-NEXT:    ret
28;
29; RV64IF-LABEL: float_test:
30; RV64IF:       # %bb.0:
31; RV64IF-NEXT:    addi sp, sp, -16
32; RV64IF-NEXT:    sd ra, 8(sp)
33; RV64IF-NEXT:    sd s0, 0(sp)
34; RV64IF-NEXT:    mv s0, a1
35; RV64IF-NEXT:    call __addsf3
36; RV64IF-NEXT:    mv a1, s0
37; RV64IF-NEXT:    call __divsf3
38; RV64IF-NEXT:    ld s0, 0(sp)
39; RV64IF-NEXT:    ld ra, 8(sp)
40; RV64IF-NEXT:    addi sp, sp, 16
41; RV64IF-NEXT:    ret
42  %1 = fadd float %a, %b
43  %2 = fdiv float %1, %b
44  ret float %2
45}
46
47define double @double_test(double %a, double %b) nounwind {
48; RV32IF-LABEL: double_test:
49; RV32IF:       # %bb.0:
50; RV32IF-NEXT:    addi sp, sp, -16
51; RV32IF-NEXT:    sw ra, 12(sp)
52; RV32IF-NEXT:    sw s0, 8(sp)
53; RV32IF-NEXT:    sw s1, 4(sp)
54; RV32IF-NEXT:    mv s0, a3
55; RV32IF-NEXT:    mv s1, a2
56; RV32IF-NEXT:    call __adddf3
57; RV32IF-NEXT:    mv a2, s1
58; RV32IF-NEXT:    mv a3, s0
59; RV32IF-NEXT:    call __divdf3
60; RV32IF-NEXT:    lw s1, 4(sp)
61; RV32IF-NEXT:    lw s0, 8(sp)
62; RV32IF-NEXT:    lw ra, 12(sp)
63; RV32IF-NEXT:    addi sp, sp, 16
64; RV32IF-NEXT:    ret
65;
66; RV64IF-LABEL: double_test:
67; RV64IF:       # %bb.0:
68; RV64IF-NEXT:    addi sp, sp, -16
69; RV64IF-NEXT:    sd ra, 8(sp)
70; RV64IF-NEXT:    sd s0, 0(sp)
71; RV64IF-NEXT:    mv s0, a1
72; RV64IF-NEXT:    call __adddf3
73; RV64IF-NEXT:    mv a1, s0
74; RV64IF-NEXT:    call __divdf3
75; RV64IF-NEXT:    ld s0, 0(sp)
76; RV64IF-NEXT:    ld ra, 8(sp)
77; RV64IF-NEXT:    addi sp, sp, 16
78; RV64IF-NEXT:    ret
79  %1 = fadd double %a, %b
80  %2 = fdiv double %1, %b
81  ret double %2
82}
83