1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
3
4; This test has multiple opportunities for SimplifyDemandedBits after type
5; legalization. There are 2 opportunities on the chain feeding the LHS of the
6; shl. And one opportunity on the shift amount. We previously weren't managing
7; the DAGCombiner worklist correctly and failed to get the RHS.
8
9define i32 @foo(i32 %x, i32 %y, i32 %z) {
10; CHECK-LABEL: foo:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    mulw a0, a0, a0
13; CHECK-NEXT:    addi a0, a0, 1
14; CHECK-NEXT:    mul a0, a0, a0
15; CHECK-NEXT:    add a0, a0, a2
16; CHECK-NEXT:    addi a0, a0, 1
17; CHECK-NEXT:    sllw a0, a0, a1
18; CHECK-NEXT:    ret
19  %b = mul i32 %x, %x
20  %c = add i32 %b, 1
21  %d = mul i32 %c, %c
22  %e = add i32 %d, %z
23  %f = add i32 %e, 1
24  %g = shl i32 %f, %y
25  ret i32 %g
26}
27