1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64I %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7; The test cases check that we use the si versions of the conversions from
8; double.
9
10define i32 @fp64_to_ui32(double %a) nounwind {
11; RV64I-LABEL: fp64_to_ui32:
12; RV64I:       # %bb.0: # %entry
13; RV64I-NEXT:    addi sp, sp, -16
14; RV64I-NEXT:    sd ra, 8(sp)
15; RV64I-NEXT:    call __fixunsdfsi
16; RV64I-NEXT:    ld ra, 8(sp)
17; RV64I-NEXT:    addi sp, sp, 16
18; RV64I-NEXT:    ret
19;
20; RV64IF-LABEL: fp64_to_ui32:
21; RV64IF:       # %bb.0: # %entry
22; RV64IF-NEXT:    addi sp, sp, -16
23; RV64IF-NEXT:    sd ra, 8(sp)
24; RV64IF-NEXT:    call __fixunsdfsi
25; RV64IF-NEXT:    ld ra, 8(sp)
26; RV64IF-NEXT:    addi sp, sp, 16
27; RV64IF-NEXT:    ret
28entry:
29  %conv = fptoui double %a to i32
30  ret i32 %conv
31}
32
33define i32 @fp64_to_si32(double %a) nounwind {
34; RV64I-LABEL: fp64_to_si32:
35; RV64I:       # %bb.0: # %entry
36; RV64I-NEXT:    addi sp, sp, -16
37; RV64I-NEXT:    sd ra, 8(sp)
38; RV64I-NEXT:    call __fixdfsi
39; RV64I-NEXT:    ld ra, 8(sp)
40; RV64I-NEXT:    addi sp, sp, 16
41; RV64I-NEXT:    ret
42;
43; RV64IF-LABEL: fp64_to_si32:
44; RV64IF:       # %bb.0: # %entry
45; RV64IF-NEXT:    addi sp, sp, -16
46; RV64IF-NEXT:    sd ra, 8(sp)
47; RV64IF-NEXT:    call __fixdfsi
48; RV64IF-NEXT:    ld ra, 8(sp)
49; RV64IF-NEXT:    addi sp, sp, 16
50; RV64IF-NEXT:    ret
51entry:
52  %conv = fptosi double %a to i32
53  ret i32 %conv
54}
55
56
57
58declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
59declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
60
61define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
62; RV64I-LABEL: strict_fp64_to_ui32:
63; RV64I:       # %bb.0: # %entry
64; RV64I-NEXT:    addi sp, sp, -16
65; RV64I-NEXT:    sd ra, 8(sp)
66; RV64I-NEXT:    call __fixunsdfsi
67; RV64I-NEXT:    ld ra, 8(sp)
68; RV64I-NEXT:    addi sp, sp, 16
69; RV64I-NEXT:    ret
70;
71; RV64IF-LABEL: strict_fp64_to_ui32:
72; RV64IF:       # %bb.0: # %entry
73; RV64IF-NEXT:    addi sp, sp, -16
74; RV64IF-NEXT:    sd ra, 8(sp)
75; RV64IF-NEXT:    call __fixunsdfsi
76; RV64IF-NEXT:    ld ra, 8(sp)
77; RV64IF-NEXT:    addi sp, sp, 16
78; RV64IF-NEXT:    ret
79entry:
80  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
81  ret i32 %conv
82}
83
84define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
85; RV64I-LABEL: struct_fp64_to_si32:
86; RV64I:       # %bb.0: # %entry
87; RV64I-NEXT:    addi sp, sp, -16
88; RV64I-NEXT:    sd ra, 8(sp)
89; RV64I-NEXT:    call __fixdfsi
90; RV64I-NEXT:    ld ra, 8(sp)
91; RV64I-NEXT:    addi sp, sp, 16
92; RV64I-NEXT:    ret
93;
94; RV64IF-LABEL: struct_fp64_to_si32:
95; RV64IF:       # %bb.0: # %entry
96; RV64IF-NEXT:    addi sp, sp, -16
97; RV64IF-NEXT:    sd ra, 8(sp)
98; RV64IF-NEXT:    call __fixdfsi
99; RV64IF-NEXT:    ld ra, 8(sp)
100; RV64IF-NEXT:    addi sp, sp, 16
101; RV64IF-NEXT:    ret
102entry:
103  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
104  ret i32 %conv
105}
106
107