1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64I
4
5; These tests must not compile to sllw/srlw/sraw, as this would be semantically
6; incorrect in the case that %b holds a value between 32 and 63. Selection
7; patterns might make the mistake of assuming that a (sext_inreg foo, i32) can
8; only be produced when sign-extending an i32 type.
9
10define i64 @tricky_shl(i64 %a, i64 %b) nounwind {
11; RV64I-LABEL: tricky_shl:
12; RV64I:       # %bb.0:
13; RV64I-NEXT:    sll a0, a0, a1
14; RV64I-NEXT:    sext.w a0, a0
15; RV64I-NEXT:    ret
16  %1 = shl i64 %a, %b
17  %2 = shl i64 %1, 32
18  %3 = ashr i64 %2, 32
19  ret i64 %3
20}
21
22define i64 @tricky_lshr(i64 %a, i64 %b) nounwind {
23; RV64I-LABEL: tricky_lshr:
24; RV64I:       # %bb.0:
25; RV64I-NEXT:    slli a0, a0, 32
26; RV64I-NEXT:    srli a0, a0, 32
27; RV64I-NEXT:    srl a0, a0, a1
28; RV64I-NEXT:    ret
29  %1 = and i64 %a, 4294967295
30  %2 = lshr i64 %1, %b
31  ret i64 %2
32}
33
34define i64 @tricky_ashr(i64 %a, i64 %b) nounwind {
35; RV64I-LABEL: tricky_ashr:
36; RV64I:       # %bb.0:
37; RV64I-NEXT:    sext.w a0, a0
38; RV64I-NEXT:    sra a0, a0, a1
39; RV64I-NEXT:    ret
40  %1 = shl i64 %a, 32
41  %2 = ashr i64 %1, 32
42  %3 = ashr i64 %2, %b
43  ret i64 %3
44}
45