1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7;; There are a few different ways to lower (select (or A, B), X, Y). This test
8;; ensures that we do so with as few branches as possible.
9
10define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
11; RV32I-LABEL: select_of_or:
12; RV32I:       # %bb.0:
13; RV32I-NEXT:    or a1, a0, a1
14; RV32I-NEXT:    mv a0, a2
15; RV32I-NEXT:    bnez a1, .LBB0_2
16; RV32I-NEXT:  # %bb.1:
17; RV32I-NEXT:    mv a0, a3
18; RV32I-NEXT:  .LBB0_2:
19; RV32I-NEXT:    ret
20;
21; RV64I-LABEL: select_of_or:
22; RV64I:       # %bb.0:
23; RV64I-NEXT:    or a1, a0, a1
24; RV64I-NEXT:    mv a0, a2
25; RV64I-NEXT:    bnez a1, .LBB0_2
26; RV64I-NEXT:  # %bb.1:
27; RV64I-NEXT:    mv a0, a3
28; RV64I-NEXT:  .LBB0_2:
29; RV64I-NEXT:    ret
30  %1 = or i1 %a, %b
31  %2 = select i1 %1, i32 %c, i32 %d
32  ret i32 %2
33}
34
35declare signext i32 @either() nounwind
36declare signext i32 @neither() nounwind
37
38define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
39; RV32I-LABEL: if_of_or:
40; RV32I:       # %bb.0:
41; RV32I-NEXT:    addi sp, sp, -16
42; RV32I-NEXT:    sw ra, 12(sp)
43; RV32I-NEXT:    or a0, a0, a1
44; RV32I-NEXT:    addi a1, zero, 1
45; RV32I-NEXT:    bne a0, a1, .LBB1_2
46; RV32I-NEXT:  # %bb.1: # %if.then
47; RV32I-NEXT:    call either
48; RV32I-NEXT:    j .LBB1_3
49; RV32I-NEXT:  .LBB1_2: # %if.else
50; RV32I-NEXT:    call neither
51; RV32I-NEXT:  .LBB1_3: # %if.end
52; RV32I-NEXT:    lw ra, 12(sp)
53; RV32I-NEXT:    addi sp, sp, 16
54; RV32I-NEXT:    ret
55;
56; RV64I-LABEL: if_of_or:
57; RV64I:       # %bb.0:
58; RV64I-NEXT:    addi sp, sp, -16
59; RV64I-NEXT:    sd ra, 8(sp)
60; RV64I-NEXT:    or a0, a0, a1
61; RV64I-NEXT:    addi a1, zero, 1
62; RV64I-NEXT:    bne a0, a1, .LBB1_2
63; RV64I-NEXT:  # %bb.1: # %if.then
64; RV64I-NEXT:    call either
65; RV64I-NEXT:    j .LBB1_3
66; RV64I-NEXT:  .LBB1_2: # %if.else
67; RV64I-NEXT:    call neither
68; RV64I-NEXT:  .LBB1_3: # %if.end
69; RV64I-NEXT:    ld ra, 8(sp)
70; RV64I-NEXT:    addi sp, sp, 16
71; RV64I-NEXT:    ret
72  %1 = or i1 %a, %b
73  br i1 %1, label %if.then, label %if.else
74
75if.then:
76  %2 = tail call i32 @either()
77  br label %if.end
78
79if.else:
80  %3 = tail call i32 @neither()
81  br label %if.end
82
83if.end:
84  %4 = phi i32 [%2, %if.then], [%3, %if.else]
85  ret i32 %4
86}
87