1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5; This test checks that unnecessary masking of shift amount operands is
6; eliminated during instruction selection. The test needs to ensure that the
7; masking is not removed if it may affect the shift amount.
8
9define i32 @sll_redundant_mask(i32 %a, i32 %b) nounwind {
10; RV32I-LABEL: sll_redundant_mask:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    sll a0, a0, a1
13; RV32I-NEXT:    ret
14  %1 = and i32 %b, 31
15  %2 = shl i32 %a, %1
16  ret i32 %2
17}
18
19define i32 @sll_non_redundant_mask(i32 %a, i32 %b) nounwind {
20; RV32I-LABEL: sll_non_redundant_mask:
21; RV32I:       # %bb.0:
22; RV32I-NEXT:    andi a1, a1, 15
23; RV32I-NEXT:    sll a0, a0, a1
24; RV32I-NEXT:    ret
25  %1 = and i32 %b, 15
26  %2 = shl i32 %a, %1
27  ret i32 %2
28}
29
30define i32 @srl_redundant_mask(i32 %a, i32 %b) nounwind {
31; RV32I-LABEL: srl_redundant_mask:
32; RV32I:       # %bb.0:
33; RV32I-NEXT:    srl a0, a0, a1
34; RV32I-NEXT:    ret
35  %1 = and i32 %b, 4095
36  %2 = lshr i32 %a, %1
37  ret i32 %2
38}
39
40define i32 @srl_non_redundant_mask(i32 %a, i32 %b) nounwind {
41; RV32I-LABEL: srl_non_redundant_mask:
42; RV32I:       # %bb.0:
43; RV32I-NEXT:    andi a1, a1, 7
44; RV32I-NEXT:    srl a0, a0, a1
45; RV32I-NEXT:    ret
46  %1 = and i32 %b, 7
47  %2 = lshr i32 %a, %1
48  ret i32 %2
49}
50
51define i32 @sra_redundant_mask(i32 %a, i32 %b) nounwind {
52; RV32I-LABEL: sra_redundant_mask:
53; RV32I:       # %bb.0:
54; RV32I-NEXT:    sra a0, a0, a1
55; RV32I-NEXT:    ret
56  %1 = and i32 %b, 65535
57  %2 = ashr i32 %a, %1
58  ret i32 %2
59}
60
61define i32 @sra_non_redundant_mask(i32 %a, i32 %b) nounwind {
62; RV32I-LABEL: sra_non_redundant_mask:
63; RV32I:       # %bb.0:
64; RV32I-NEXT:    andi a1, a1, 32
65; RV32I-NEXT:    sra a0, a0, a1
66; RV32I-NEXT:    ret
67  %1 = and i32 %b, 32
68  %2 = ashr i32 %a, %1
69  ret i32 %2
70}
71