1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7declare void @callee(i8*, i32*)
8
9define void @caller(i32 %n) {
10; RV32I-LABEL: caller:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    addi sp, sp, -128
13; RV32I-NEXT:    .cfi_def_cfa_offset 128
14; RV32I-NEXT:    sw ra, 124(sp)
15; RV32I-NEXT:    sw s0, 120(sp)
16; RV32I-NEXT:    sw s1, 116(sp)
17; RV32I-NEXT:    .cfi_offset ra, -4
18; RV32I-NEXT:    .cfi_offset s0, -8
19; RV32I-NEXT:    .cfi_offset s1, -12
20; RV32I-NEXT:    addi s0, sp, 128
21; RV32I-NEXT:    .cfi_def_cfa s0, 0
22; RV32I-NEXT:    andi sp, sp, -64
23; RV32I-NEXT:    mv s1, sp
24; RV32I-NEXT:    addi a0, a0, 15
25; RV32I-NEXT:    andi a0, a0, -16
26; RV32I-NEXT:    sub a0, sp, a0
27; RV32I-NEXT:    mv sp, a0
28; RV32I-NEXT:    addi a1, s1, 64
29; RV32I-NEXT:    call callee
30; RV32I-NEXT:    addi sp, s0, -128
31; RV32I-NEXT:    lw s1, 116(sp)
32; RV32I-NEXT:    lw s0, 120(sp)
33; RV32I-NEXT:    lw ra, 124(sp)
34; RV32I-NEXT:    addi sp, sp, 128
35; RV32I-NEXT:    ret
36;
37; RV64I-LABEL: caller:
38; RV64I:       # %bb.0:
39; RV64I-NEXT:    addi sp, sp, -128
40; RV64I-NEXT:    .cfi_def_cfa_offset 128
41; RV64I-NEXT:    sd ra, 120(sp)
42; RV64I-NEXT:    sd s0, 112(sp)
43; RV64I-NEXT:    sd s1, 104(sp)
44; RV64I-NEXT:    .cfi_offset ra, -8
45; RV64I-NEXT:    .cfi_offset s0, -16
46; RV64I-NEXT:    .cfi_offset s1, -24
47; RV64I-NEXT:    addi s0, sp, 128
48; RV64I-NEXT:    .cfi_def_cfa s0, 0
49; RV64I-NEXT:    andi sp, sp, -64
50; RV64I-NEXT:    mv s1, sp
51; RV64I-NEXT:    slli a0, a0, 32
52; RV64I-NEXT:    srli a0, a0, 32
53; RV64I-NEXT:    addi a0, a0, 15
54; RV64I-NEXT:    addi a1, zero, 1
55; RV64I-NEXT:    slli a1, a1, 33
56; RV64I-NEXT:    addi a1, a1, -16
57; RV64I-NEXT:    and a0, a0, a1
58; RV64I-NEXT:    sub a0, sp, a0
59; RV64I-NEXT:    mv sp, a0
60; RV64I-NEXT:    addi a1, s1, 64
61; RV64I-NEXT:    call callee
62; RV64I-NEXT:    addi sp, s0, -128
63; RV64I-NEXT:    ld s1, 104(sp)
64; RV64I-NEXT:    ld s0, 112(sp)
65; RV64I-NEXT:    ld ra, 120(sp)
66; RV64I-NEXT:    addi sp, sp, 128
67; RV64I-NEXT:    ret
68  %1 = alloca i8, i32 %n
69  %2 = alloca i32, align 64
70  call void @callee(i8* %1, i32 *%2)
71  ret void
72}
73