1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7declare void @callee(i8*)
8
9define void @caller32() nounwind {
10; RV32I-LABEL: caller32:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    addi sp, sp, -64
13; RV32I-NEXT:    sw ra, 60(sp)
14; RV32I-NEXT:    sw s0, 56(sp)
15; RV32I-NEXT:    addi s0, sp, 64
16; RV32I-NEXT:    andi sp, sp, -32
17; RV32I-NEXT:    addi a0, sp, 32
18; RV32I-NEXT:    call callee
19; RV32I-NEXT:    addi sp, s0, -64
20; RV32I-NEXT:    lw s0, 56(sp)
21; RV32I-NEXT:    lw ra, 60(sp)
22; RV32I-NEXT:    addi sp, sp, 64
23; RV32I-NEXT:    ret
24;
25; RV64I-LABEL: caller32:
26; RV64I:       # %bb.0:
27; RV64I-NEXT:    addi sp, sp, -64
28; RV64I-NEXT:    sd ra, 56(sp)
29; RV64I-NEXT:    sd s0, 48(sp)
30; RV64I-NEXT:    addi s0, sp, 64
31; RV64I-NEXT:    andi sp, sp, -32
32; RV64I-NEXT:    addi a0, sp, 32
33; RV64I-NEXT:    call callee
34; RV64I-NEXT:    addi sp, s0, -64
35; RV64I-NEXT:    ld s0, 48(sp)
36; RV64I-NEXT:    ld ra, 56(sp)
37; RV64I-NEXT:    addi sp, sp, 64
38; RV64I-NEXT:    ret
39  %1 = alloca i8, align 32
40  call void @callee(i8* %1)
41  ret void
42}
43
44define void @caller_no_realign32() nounwind "no-realign-stack" {
45; RV32I-LABEL: caller_no_realign32:
46; RV32I:       # %bb.0:
47; RV32I-NEXT:    addi sp, sp, -16
48; RV32I-NEXT:    sw ra, 12(sp)
49; RV32I-NEXT:    mv a0, sp
50; RV32I-NEXT:    call callee
51; RV32I-NEXT:    lw ra, 12(sp)
52; RV32I-NEXT:    addi sp, sp, 16
53; RV32I-NEXT:    ret
54;
55; RV64I-LABEL: caller_no_realign32:
56; RV64I:       # %bb.0:
57; RV64I-NEXT:    addi sp, sp, -16
58; RV64I-NEXT:    sd ra, 8(sp)
59; RV64I-NEXT:    mv a0, sp
60; RV64I-NEXT:    call callee
61; RV64I-NEXT:    ld ra, 8(sp)
62; RV64I-NEXT:    addi sp, sp, 16
63; RV64I-NEXT:    ret
64  %1 = alloca i8, align 32
65  call void @callee(i8* %1)
66  ret void
67}
68
69define void @caller64() nounwind {
70; RV32I-LABEL: caller64:
71; RV32I:       # %bb.0:
72; RV32I-NEXT:    addi sp, sp, -128
73; RV32I-NEXT:    sw ra, 124(sp)
74; RV32I-NEXT:    sw s0, 120(sp)
75; RV32I-NEXT:    addi s0, sp, 128
76; RV32I-NEXT:    andi sp, sp, -64
77; RV32I-NEXT:    addi a0, sp, 64
78; RV32I-NEXT:    call callee
79; RV32I-NEXT:    addi sp, s0, -128
80; RV32I-NEXT:    lw s0, 120(sp)
81; RV32I-NEXT:    lw ra, 124(sp)
82; RV32I-NEXT:    addi sp, sp, 128
83; RV32I-NEXT:    ret
84;
85; RV64I-LABEL: caller64:
86; RV64I:       # %bb.0:
87; RV64I-NEXT:    addi sp, sp, -128
88; RV64I-NEXT:    sd ra, 120(sp)
89; RV64I-NEXT:    sd s0, 112(sp)
90; RV64I-NEXT:    addi s0, sp, 128
91; RV64I-NEXT:    andi sp, sp, -64
92; RV64I-NEXT:    addi a0, sp, 64
93; RV64I-NEXT:    call callee
94; RV64I-NEXT:    addi sp, s0, -128
95; RV64I-NEXT:    ld s0, 112(sp)
96; RV64I-NEXT:    ld ra, 120(sp)
97; RV64I-NEXT:    addi sp, sp, 128
98; RV64I-NEXT:    ret
99  %1 = alloca i8, align 64
100  call void @callee(i8* %1)
101  ret void
102}
103
104define void @caller_no_realign64() nounwind "no-realign-stack" {
105; RV32I-LABEL: caller_no_realign64:
106; RV32I:       # %bb.0:
107; RV32I-NEXT:    addi sp, sp, -16
108; RV32I-NEXT:    sw ra, 12(sp)
109; RV32I-NEXT:    mv a0, sp
110; RV32I-NEXT:    call callee
111; RV32I-NEXT:    lw ra, 12(sp)
112; RV32I-NEXT:    addi sp, sp, 16
113; RV32I-NEXT:    ret
114;
115; RV64I-LABEL: caller_no_realign64:
116; RV64I:       # %bb.0:
117; RV64I-NEXT:    addi sp, sp, -16
118; RV64I-NEXT:    sd ra, 8(sp)
119; RV64I-NEXT:    mv a0, sp
120; RV64I-NEXT:    call callee
121; RV64I-NEXT:    ld ra, 8(sp)
122; RV64I-NEXT:    addi sp, sp, 16
123; RV64I-NEXT:    ret
124  %1 = alloca i8, align 64
125  call void @callee(i8* %1)
126  ret void
127}
128
129define void @caller128() nounwind {
130; RV32I-LABEL: caller128:
131; RV32I:       # %bb.0:
132; RV32I-NEXT:    addi sp, sp, -256
133; RV32I-NEXT:    sw ra, 252(sp)
134; RV32I-NEXT:    sw s0, 248(sp)
135; RV32I-NEXT:    addi s0, sp, 256
136; RV32I-NEXT:    andi sp, sp, -128
137; RV32I-NEXT:    addi a0, sp, 128
138; RV32I-NEXT:    call callee
139; RV32I-NEXT:    addi sp, s0, -256
140; RV32I-NEXT:    lw s0, 248(sp)
141; RV32I-NEXT:    lw ra, 252(sp)
142; RV32I-NEXT:    addi sp, sp, 256
143; RV32I-NEXT:    ret
144;
145; RV64I-LABEL: caller128:
146; RV64I:       # %bb.0:
147; RV64I-NEXT:    addi sp, sp, -256
148; RV64I-NEXT:    sd ra, 248(sp)
149; RV64I-NEXT:    sd s0, 240(sp)
150; RV64I-NEXT:    addi s0, sp, 256
151; RV64I-NEXT:    andi sp, sp, -128
152; RV64I-NEXT:    addi a0, sp, 128
153; RV64I-NEXT:    call callee
154; RV64I-NEXT:    addi sp, s0, -256
155; RV64I-NEXT:    ld s0, 240(sp)
156; RV64I-NEXT:    ld ra, 248(sp)
157; RV64I-NEXT:    addi sp, sp, 256
158; RV64I-NEXT:    ret
159  %1 = alloca i8, align 128
160  call void @callee(i8* %1)
161  ret void
162}
163
164define void @caller_no_realign128() nounwind "no-realign-stack" {
165; RV32I-LABEL: caller_no_realign128:
166; RV32I:       # %bb.0:
167; RV32I-NEXT:    addi sp, sp, -16
168; RV32I-NEXT:    sw ra, 12(sp)
169; RV32I-NEXT:    mv a0, sp
170; RV32I-NEXT:    call callee
171; RV32I-NEXT:    lw ra, 12(sp)
172; RV32I-NEXT:    addi sp, sp, 16
173; RV32I-NEXT:    ret
174;
175; RV64I-LABEL: caller_no_realign128:
176; RV64I:       # %bb.0:
177; RV64I-NEXT:    addi sp, sp, -16
178; RV64I-NEXT:    sd ra, 8(sp)
179; RV64I-NEXT:    mv a0, sp
180; RV64I-NEXT:    call callee
181; RV64I-NEXT:    ld ra, 8(sp)
182; RV64I-NEXT:    addi sp, sp, 16
183; RV64I-NEXT:    ret
184  %1 = alloca i8, align 128
185  call void @callee(i8* %1)
186  ret void
187}
188
189define void @caller256() nounwind {
190; RV32I-LABEL: caller256:
191; RV32I:       # %bb.0:
192; RV32I-NEXT:    addi sp, sp, -512
193; RV32I-NEXT:    sw ra, 508(sp)
194; RV32I-NEXT:    sw s0, 504(sp)
195; RV32I-NEXT:    addi s0, sp, 512
196; RV32I-NEXT:    andi sp, sp, -256
197; RV32I-NEXT:    addi a0, sp, 256
198; RV32I-NEXT:    call callee
199; RV32I-NEXT:    addi sp, s0, -512
200; RV32I-NEXT:    lw s0, 504(sp)
201; RV32I-NEXT:    lw ra, 508(sp)
202; RV32I-NEXT:    addi sp, sp, 512
203; RV32I-NEXT:    ret
204;
205; RV64I-LABEL: caller256:
206; RV64I:       # %bb.0:
207; RV64I-NEXT:    addi sp, sp, -512
208; RV64I-NEXT:    sd ra, 504(sp)
209; RV64I-NEXT:    sd s0, 496(sp)
210; RV64I-NEXT:    addi s0, sp, 512
211; RV64I-NEXT:    andi sp, sp, -256
212; RV64I-NEXT:    addi a0, sp, 256
213; RV64I-NEXT:    call callee
214; RV64I-NEXT:    addi sp, s0, -512
215; RV64I-NEXT:    ld s0, 496(sp)
216; RV64I-NEXT:    ld ra, 504(sp)
217; RV64I-NEXT:    addi sp, sp, 512
218; RV64I-NEXT:    ret
219  %1 = alloca i8, align 256
220  call void @callee(i8* %1)
221  ret void
222}
223
224define void @caller_no_realign256() nounwind "no-realign-stack" {
225; RV32I-LABEL: caller_no_realign256:
226; RV32I:       # %bb.0:
227; RV32I-NEXT:    addi sp, sp, -16
228; RV32I-NEXT:    sw ra, 12(sp)
229; RV32I-NEXT:    mv a0, sp
230; RV32I-NEXT:    call callee
231; RV32I-NEXT:    lw ra, 12(sp)
232; RV32I-NEXT:    addi sp, sp, 16
233; RV32I-NEXT:    ret
234;
235; RV64I-LABEL: caller_no_realign256:
236; RV64I:       # %bb.0:
237; RV64I-NEXT:    addi sp, sp, -16
238; RV64I-NEXT:    sd ra, 8(sp)
239; RV64I-NEXT:    mv a0, sp
240; RV64I-NEXT:    call callee
241; RV64I-NEXT:    ld ra, 8(sp)
242; RV64I-NEXT:    addi sp, sp, 16
243; RV64I-NEXT:    ret
244  %1 = alloca i8, align 256
245  call void @callee(i8* %1)
246  ret void
247}
248
249define void @caller512() nounwind {
250; RV32I-LABEL: caller512:
251; RV32I:       # %bb.0:
252; RV32I-NEXT:    addi sp, sp, -1536
253; RV32I-NEXT:    sw ra, 1532(sp)
254; RV32I-NEXT:    sw s0, 1528(sp)
255; RV32I-NEXT:    addi s0, sp, 1536
256; RV32I-NEXT:    andi sp, sp, -512
257; RV32I-NEXT:    addi a0, sp, 1024
258; RV32I-NEXT:    call callee
259; RV32I-NEXT:    addi sp, s0, -1536
260; RV32I-NEXT:    lw s0, 1528(sp)
261; RV32I-NEXT:    lw ra, 1532(sp)
262; RV32I-NEXT:    addi sp, sp, 1536
263; RV32I-NEXT:    ret
264;
265; RV64I-LABEL: caller512:
266; RV64I:       # %bb.0:
267; RV64I-NEXT:    addi sp, sp, -1536
268; RV64I-NEXT:    sd ra, 1528(sp)
269; RV64I-NEXT:    sd s0, 1520(sp)
270; RV64I-NEXT:    addi s0, sp, 1536
271; RV64I-NEXT:    andi sp, sp, -512
272; RV64I-NEXT:    addi a0, sp, 1024
273; RV64I-NEXT:    call callee
274; RV64I-NEXT:    addi sp, s0, -1536
275; RV64I-NEXT:    ld s0, 1520(sp)
276; RV64I-NEXT:    ld ra, 1528(sp)
277; RV64I-NEXT:    addi sp, sp, 1536
278; RV64I-NEXT:    ret
279  %1 = alloca i8, align 512
280  call void @callee(i8* %1)
281  ret void
282}
283
284define void @caller_no_realign512() nounwind "no-realign-stack" {
285; RV32I-LABEL: caller_no_realign512:
286; RV32I:       # %bb.0:
287; RV32I-NEXT:    addi sp, sp, -16
288; RV32I-NEXT:    sw ra, 12(sp)
289; RV32I-NEXT:    mv a0, sp
290; RV32I-NEXT:    call callee
291; RV32I-NEXT:    lw ra, 12(sp)
292; RV32I-NEXT:    addi sp, sp, 16
293; RV32I-NEXT:    ret
294;
295; RV64I-LABEL: caller_no_realign512:
296; RV64I:       # %bb.0:
297; RV64I-NEXT:    addi sp, sp, -16
298; RV64I-NEXT:    sd ra, 8(sp)
299; RV64I-NEXT:    mv a0, sp
300; RV64I-NEXT:    call callee
301; RV64I-NEXT:    ld ra, 8(sp)
302; RV64I-NEXT:    addi sp, sp, 16
303; RV64I-NEXT:    ret
304  %1 = alloca i8, align 512
305  call void @callee(i8* %1)
306  ret void
307}
308
309define void @caller1024() nounwind {
310; RV32I-LABEL: caller1024:
311; RV32I:       # %bb.0:
312; RV32I-NEXT:    addi sp, sp, -2032
313; RV32I-NEXT:    sw ra, 2028(sp)
314; RV32I-NEXT:    sw s0, 2024(sp)
315; RV32I-NEXT:    addi s0, sp, 2032
316; RV32I-NEXT:    addi sp, sp, -1040
317; RV32I-NEXT:    andi sp, sp, -1024
318; RV32I-NEXT:    lui a0, 1
319; RV32I-NEXT:    addi a0, a0, -2048
320; RV32I-NEXT:    add a0, sp, a0
321; RV32I-NEXT:    mv a0, a0
322; RV32I-NEXT:    call callee
323; RV32I-NEXT:    lui a0, 1
324; RV32I-NEXT:    addi a0, a0, -1024
325; RV32I-NEXT:    sub sp, s0, a0
326; RV32I-NEXT:    addi sp, sp, 1040
327; RV32I-NEXT:    lw s0, 2024(sp)
328; RV32I-NEXT:    lw ra, 2028(sp)
329; RV32I-NEXT:    addi sp, sp, 2032
330; RV32I-NEXT:    ret
331;
332; RV64I-LABEL: caller1024:
333; RV64I:       # %bb.0:
334; RV64I-NEXT:    addi sp, sp, -2032
335; RV64I-NEXT:    sd ra, 2024(sp)
336; RV64I-NEXT:    sd s0, 2016(sp)
337; RV64I-NEXT:    addi s0, sp, 2032
338; RV64I-NEXT:    addi sp, sp, -1040
339; RV64I-NEXT:    andi sp, sp, -1024
340; RV64I-NEXT:    lui a0, 1
341; RV64I-NEXT:    addiw a0, a0, -2048
342; RV64I-NEXT:    add a0, sp, a0
343; RV64I-NEXT:    mv a0, a0
344; RV64I-NEXT:    call callee
345; RV64I-NEXT:    lui a0, 1
346; RV64I-NEXT:    addiw a0, a0, -1024
347; RV64I-NEXT:    sub sp, s0, a0
348; RV64I-NEXT:    addi sp, sp, 1040
349; RV64I-NEXT:    ld s0, 2016(sp)
350; RV64I-NEXT:    ld ra, 2024(sp)
351; RV64I-NEXT:    addi sp, sp, 2032
352; RV64I-NEXT:    ret
353  %1 = alloca i8, align 1024
354  call void @callee(i8* %1)
355  ret void
356}
357
358define void @caller_no_realign1024() nounwind "no-realign-stack" {
359; RV32I-LABEL: caller_no_realign1024:
360; RV32I:       # %bb.0:
361; RV32I-NEXT:    addi sp, sp, -16
362; RV32I-NEXT:    sw ra, 12(sp)
363; RV32I-NEXT:    mv a0, sp
364; RV32I-NEXT:    call callee
365; RV32I-NEXT:    lw ra, 12(sp)
366; RV32I-NEXT:    addi sp, sp, 16
367; RV32I-NEXT:    ret
368;
369; RV64I-LABEL: caller_no_realign1024:
370; RV64I:       # %bb.0:
371; RV64I-NEXT:    addi sp, sp, -16
372; RV64I-NEXT:    sd ra, 8(sp)
373; RV64I-NEXT:    mv a0, sp
374; RV64I-NEXT:    call callee
375; RV64I-NEXT:    ld ra, 8(sp)
376; RV64I-NEXT:    addi sp, sp, 16
377; RV64I-NEXT:    ret
378  %1 = alloca i8, align 1024
379  call void @callee(i8* %1)
380  ret void
381}
382
383define void @caller2048() nounwind {
384; RV32I-LABEL: caller2048:
385; RV32I:       # %bb.0:
386; RV32I-NEXT:    addi sp, sp, -2032
387; RV32I-NEXT:    sw ra, 2028(sp)
388; RV32I-NEXT:    sw s0, 2024(sp)
389; RV32I-NEXT:    addi s0, sp, 2032
390; RV32I-NEXT:    lui a0, 1
391; RV32I-NEXT:    addi a0, a0, 16
392; RV32I-NEXT:    sub sp, sp, a0
393; RV32I-NEXT:    andi sp, sp, -2048
394; RV32I-NEXT:    lui a0, 1
395; RV32I-NEXT:    add a0, sp, a0
396; RV32I-NEXT:    mv a0, a0
397; RV32I-NEXT:    call callee
398; RV32I-NEXT:    lui a0, 2
399; RV32I-NEXT:    addi a0, a0, -2048
400; RV32I-NEXT:    sub sp, s0, a0
401; RV32I-NEXT:    lui a0, 1
402; RV32I-NEXT:    addi a0, a0, 16
403; RV32I-NEXT:    add sp, sp, a0
404; RV32I-NEXT:    lw s0, 2024(sp)
405; RV32I-NEXT:    lw ra, 2028(sp)
406; RV32I-NEXT:    addi sp, sp, 2032
407; RV32I-NEXT:    ret
408;
409; RV64I-LABEL: caller2048:
410; RV64I:       # %bb.0:
411; RV64I-NEXT:    addi sp, sp, -2032
412; RV64I-NEXT:    sd ra, 2024(sp)
413; RV64I-NEXT:    sd s0, 2016(sp)
414; RV64I-NEXT:    addi s0, sp, 2032
415; RV64I-NEXT:    lui a0, 1
416; RV64I-NEXT:    addiw a0, a0, 16
417; RV64I-NEXT:    sub sp, sp, a0
418; RV64I-NEXT:    andi sp, sp, -2048
419; RV64I-NEXT:    lui a0, 1
420; RV64I-NEXT:    add a0, sp, a0
421; RV64I-NEXT:    mv a0, a0
422; RV64I-NEXT:    call callee
423; RV64I-NEXT:    lui a0, 2
424; RV64I-NEXT:    addiw a0, a0, -2048
425; RV64I-NEXT:    sub sp, s0, a0
426; RV64I-NEXT:    lui a0, 1
427; RV64I-NEXT:    addiw a0, a0, 16
428; RV64I-NEXT:    add sp, sp, a0
429; RV64I-NEXT:    ld s0, 2016(sp)
430; RV64I-NEXT:    ld ra, 2024(sp)
431; RV64I-NEXT:    addi sp, sp, 2032
432; RV64I-NEXT:    ret
433  %1 = alloca i8, align 2048
434  call void @callee(i8* %1)
435  ret void
436}
437
438define void @caller_no_realign2048() nounwind "no-realign-stack" {
439; RV32I-LABEL: caller_no_realign2048:
440; RV32I:       # %bb.0:
441; RV32I-NEXT:    addi sp, sp, -16
442; RV32I-NEXT:    sw ra, 12(sp)
443; RV32I-NEXT:    mv a0, sp
444; RV32I-NEXT:    call callee
445; RV32I-NEXT:    lw ra, 12(sp)
446; RV32I-NEXT:    addi sp, sp, 16
447; RV32I-NEXT:    ret
448;
449; RV64I-LABEL: caller_no_realign2048:
450; RV64I:       # %bb.0:
451; RV64I-NEXT:    addi sp, sp, -16
452; RV64I-NEXT:    sd ra, 8(sp)
453; RV64I-NEXT:    mv a0, sp
454; RV64I-NEXT:    call callee
455; RV64I-NEXT:    ld ra, 8(sp)
456; RV64I-NEXT:    addi sp, sp, 16
457; RV64I-NEXT:    ret
458  %1 = alloca i8, align 2048
459  call void @callee(i8* %1)
460  ret void
461}
462
463define void @caller4096() nounwind {
464; RV32I-LABEL: caller4096:
465; RV32I:       # %bb.0:
466; RV32I-NEXT:    addi sp, sp, -2032
467; RV32I-NEXT:    sw ra, 2028(sp)
468; RV32I-NEXT:    sw s0, 2024(sp)
469; RV32I-NEXT:    addi s0, sp, 2032
470; RV32I-NEXT:    lui a0, 3
471; RV32I-NEXT:    addi a0, a0, -2032
472; RV32I-NEXT:    sub sp, sp, a0
473; RV32I-NEXT:    srli a0, sp, 12
474; RV32I-NEXT:    slli sp, a0, 12
475; RV32I-NEXT:    lui a0, 2
476; RV32I-NEXT:    add a0, sp, a0
477; RV32I-NEXT:    mv a0, a0
478; RV32I-NEXT:    call callee
479; RV32I-NEXT:    lui a0, 3
480; RV32I-NEXT:    sub sp, s0, a0
481; RV32I-NEXT:    lui a0, 3
482; RV32I-NEXT:    addi a0, a0, -2032
483; RV32I-NEXT:    add sp, sp, a0
484; RV32I-NEXT:    lw s0, 2024(sp)
485; RV32I-NEXT:    lw ra, 2028(sp)
486; RV32I-NEXT:    addi sp, sp, 2032
487; RV32I-NEXT:    ret
488;
489; RV64I-LABEL: caller4096:
490; RV64I:       # %bb.0:
491; RV64I-NEXT:    addi sp, sp, -2032
492; RV64I-NEXT:    sd ra, 2024(sp)
493; RV64I-NEXT:    sd s0, 2016(sp)
494; RV64I-NEXT:    addi s0, sp, 2032
495; RV64I-NEXT:    lui a0, 3
496; RV64I-NEXT:    addiw a0, a0, -2032
497; RV64I-NEXT:    sub sp, sp, a0
498; RV64I-NEXT:    srli a0, sp, 12
499; RV64I-NEXT:    slli sp, a0, 12
500; RV64I-NEXT:    lui a0, 2
501; RV64I-NEXT:    add a0, sp, a0
502; RV64I-NEXT:    mv a0, a0
503; RV64I-NEXT:    call callee
504; RV64I-NEXT:    lui a0, 3
505; RV64I-NEXT:    sub sp, s0, a0
506; RV64I-NEXT:    lui a0, 3
507; RV64I-NEXT:    addiw a0, a0, -2032
508; RV64I-NEXT:    add sp, sp, a0
509; RV64I-NEXT:    ld s0, 2016(sp)
510; RV64I-NEXT:    ld ra, 2024(sp)
511; RV64I-NEXT:    addi sp, sp, 2032
512; RV64I-NEXT:    ret
513  %1 = alloca i8, align 4096
514  call void @callee(i8* %1)
515  ret void
516}
517
518define void @caller_no_realign4096() nounwind "no-realign-stack" {
519; RV32I-LABEL: caller_no_realign4096:
520; RV32I:       # %bb.0:
521; RV32I-NEXT:    addi sp, sp, -16
522; RV32I-NEXT:    sw ra, 12(sp)
523; RV32I-NEXT:    mv a0, sp
524; RV32I-NEXT:    call callee
525; RV32I-NEXT:    lw ra, 12(sp)
526; RV32I-NEXT:    addi sp, sp, 16
527; RV32I-NEXT:    ret
528;
529; RV64I-LABEL: caller_no_realign4096:
530; RV64I:       # %bb.0:
531; RV64I-NEXT:    addi sp, sp, -16
532; RV64I-NEXT:    sd ra, 8(sp)
533; RV64I-NEXT:    mv a0, sp
534; RV64I-NEXT:    call callee
535; RV64I-NEXT:    ld ra, 8(sp)
536; RV64I-NEXT:    addi sp, sp, 16
537; RV64I-NEXT:    ret
538  %1 = alloca i8, align 4096
539  call void @callee(i8* %1)
540  ret void
541}
542