1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;
3; Test that DAGCombiner does not produce an addcarry node if the carry
4; producer is not legal. This can happen e.g. with an uaddo with a type
5; that is not legal.
6;
7; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
8
9define void @fun(i16 %arg0, i16* %src, i32* %dst) {
10; CHECK-LABEL: fun:
11; CHECK:       # %bb.0: # %bb
12; CHECK-NEXT:    llhr %r0, %r2
13; CHECK-NEXT:    llh %r2, 0(%r3)
14; CHECK-NEXT:    chi %r0, 9616
15; CHECK-NEXT:    lhi %r1, 0
16; CHECK-NEXT:    lochil %r1, 1
17; CHECK-NEXT:    afi %r2, 65535
18; CHECK-NEXT:    llhr %r3, %r2
19; CHECK-NEXT:    lhi %r0, 0
20; CHECK-NEXT:    cr %r3, %r2
21; CHECK-NEXT:    lochilh %r0, 1
22; CHECK-NEXT:    ar %r0, %r1
23; CHECK-NEXT:    st %r0, 0(%r4)
24; CHECK-NEXT:    br %r14
25bb:
26  %tmp = icmp ult i16 %arg0, 9616
27  %tmp1 = zext i1 %tmp to i32
28  %tmp2 = load i16, i16* %src
29  %0 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %tmp2, i16 -1)
30  %math = extractvalue { i16, i1 } %0, 0
31  %ov = extractvalue { i16, i1 } %0, 1
32  %tmp5 = zext i1 %ov to i32
33  %tmp6 = add nuw nsw i32 %tmp5, %tmp1
34  store i32 %tmp6, i32* %dst
35  ret void
36}
37
38declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
39