1; Test 64-bit addition in which the second operand is variable.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s --check-prefixes=CHECK,Z10
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefixes=CHECK,Z196
5
6declare i64 @foo()
7
8; Check AGR.
9define i64 @f1(i64 %a, i64 %b) {
10; CHECK-LABEL: f1:
11; CHECK: agr %r2, %r3
12; CHECK: br %r14
13  %add = add i64 %a, %b
14  ret i64 %add
15}
16
17; Check AG with no displacement.
18define i64 @f2(i64 %a, i64 *%src) {
19; CHECK-LABEL: f2:
20; CHECK: ag %r2, 0(%r3)
21; CHECK: br %r14
22  %b = load i64, i64 *%src
23  %add = add i64 %a, %b
24  ret i64 %add
25}
26
27; Check the high end of the aligned AG range.
28define i64 @f3(i64 %a, i64 *%src) {
29; CHECK-LABEL: f3:
30; CHECK: ag %r2, 524280(%r3)
31; CHECK: br %r14
32  %ptr = getelementptr i64, i64 *%src, i64 65535
33  %b = load i64, i64 *%ptr
34  %add = add i64 %a, %b
35  ret i64 %add
36}
37
38; Check the next doubleword up, which needs separate address logic.
39; Other sequences besides this one would be OK.
40define i64 @f4(i64 %a, i64 *%src) {
41; CHECK-LABEL: f4:
42; CHECK: agfi %r3, 524288
43; CHECK: ag %r2, 0(%r3)
44; CHECK: br %r14
45  %ptr = getelementptr i64, i64 *%src, i64 65536
46  %b = load i64, i64 *%ptr
47  %add = add i64 %a, %b
48  ret i64 %add
49}
50
51; Check the high end of the negative aligned AG range.
52define i64 @f5(i64 %a, i64 *%src) {
53; CHECK-LABEL: f5:
54; CHECK: ag %r2, -8(%r3)
55; CHECK: br %r14
56  %ptr = getelementptr i64, i64 *%src, i64 -1
57  %b = load i64, i64 *%ptr
58  %add = add i64 %a, %b
59  ret i64 %add
60}
61
62; Check the low end of the AG range.
63define i64 @f6(i64 %a, i64 *%src) {
64; CHECK-LABEL: f6:
65; CHECK: ag %r2, -524288(%r3)
66; CHECK: br %r14
67  %ptr = getelementptr i64, i64 *%src, i64 -65536
68  %b = load i64, i64 *%ptr
69  %add = add i64 %a, %b
70  ret i64 %add
71}
72
73; Check the next doubleword down, which needs separate address logic.
74; Other sequences besides this one would be OK.
75define i64 @f7(i64 %a, i64 *%src) {
76; CHECK-LABEL: f7:
77; CHECK: agfi %r3, -524296
78; CHECK: ag %r2, 0(%r3)
79; CHECK: br %r14
80  %ptr = getelementptr i64, i64 *%src, i64 -65537
81  %b = load i64, i64 *%ptr
82  %add = add i64 %a, %b
83  ret i64 %add
84}
85
86; Check that AG allows an index.
87define i64 @f8(i64 %a, i64 %src, i64 %index) {
88; CHECK-LABEL: f8:
89; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
90; CHECK: br %r14
91  %add1 = add i64 %src, %index
92  %add2 = add i64 %add1, 524280
93  %ptr = inttoptr i64 %add2 to i64 *
94  %b = load i64, i64 *%ptr
95  %add = add i64 %a, %b
96  ret i64 %add
97}
98
99; Check that additions of spilled values can use AG rather than AGR.
100; Note: Z196 is suboptimal with one unfolded reload.
101define i64 @f9(i64 *%ptr0) {
102; CHECK-LABEL: f9:
103; CHECK: brasl %r14, foo@PLT
104; Z10:  ag %r2, 168(%r15)
105; Z196: ag %r0, 168(%r15)
106; CHECK: br %r14
107  %ptr1 = getelementptr i64, i64 *%ptr0, i64 2
108  %ptr2 = getelementptr i64, i64 *%ptr0, i64 4
109  %ptr3 = getelementptr i64, i64 *%ptr0, i64 6
110  %ptr4 = getelementptr i64, i64 *%ptr0, i64 8
111  %ptr5 = getelementptr i64, i64 *%ptr0, i64 10
112  %ptr6 = getelementptr i64, i64 *%ptr0, i64 12
113  %ptr7 = getelementptr i64, i64 *%ptr0, i64 14
114  %ptr8 = getelementptr i64, i64 *%ptr0, i64 16
115  %ptr9 = getelementptr i64, i64 *%ptr0, i64 18
116
117  %val0 = load i64, i64 *%ptr0
118  %val1 = load i64, i64 *%ptr1
119  %val2 = load i64, i64 *%ptr2
120  %val3 = load i64, i64 *%ptr3
121  %val4 = load i64, i64 *%ptr4
122  %val5 = load i64, i64 *%ptr5
123  %val6 = load i64, i64 *%ptr6
124  %val7 = load i64, i64 *%ptr7
125  %val8 = load i64, i64 *%ptr8
126  %val9 = load i64, i64 *%ptr9
127
128  %ret = call i64 @foo()
129
130  %add0 = add i64 %ret, %val0
131  %add1 = add i64 %add0, %val1
132  %add2 = add i64 %add1, %val2
133  %add3 = add i64 %add2, %val3
134  %add4 = add i64 %add3, %val4
135  %add5 = add i64 %add4, %val5
136  %add6 = add i64 %add5, %val6
137  %add7 = add i64 %add6, %val7
138  %add8 = add i64 %add7, %val8
139  %add9 = add i64 %add8, %val9
140
141  ret i64 %add9
142}
143