1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test use of RISBG vs RISBGN on zEC12.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
5
6; On zEC12, we generally prefer RISBGN.
7define i64 @f1(i64 %a, i64 %b) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    risbgn %r2, %r3, 60, 62, 0
11; CHECK-NEXT:    br %r14
12  %anda = and i64 %a, -15
13  %andb = and i64 %b, 14
14  %or = or i64 %anda, %andb
15  ret i64 %or
16}
17
18; But we may fall back to RISBG if we can use the condition code.
19define i64 @f2(i64 %a, i64 %b, i32* %c) {
20; CHECK-LABEL: f2:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    risbg %r2, %r3, 60, 62, 0
23; CHECK-NEXT:    ipm %r0
24; CHECK-NEXT:    risblg %r0, %r0, 31, 159, 35
25; CHECK-NEXT:    st %r0, 0(%r4)
26; CHECK-NEXT:    br %r14
27  %anda = and i64 %a, -15
28  %andb = and i64 %b, 14
29  %or = or i64 %anda, %andb
30  %cmp = icmp sgt i64 %or, 0
31  %conv = zext i1 %cmp to i32
32  store i32 %conv, i32* %c, align 4
33  ret i64 %or
34}
35
36