1; Test strict vector addition on z14.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
4
5declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
6declare <4 x float> @llvm.experimental.constrained.fadd.v4f32(<4 x float>, <4 x float>, metadata, metadata)
7
8; Test a v4f32 addition.
9define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
10                       <4 x float> %val2) strictfp {
11; CHECK-LABEL: f1:
12; CHECK: vfasb %v24, %v26, %v28
13; CHECK: br %r14
14  %ret = call <4 x float> @llvm.experimental.constrained.fadd.v4f32(
15                        <4 x float> %val1, <4 x float> %val2,
16                        metadata !"round.dynamic",
17                        metadata !"fpexcept.strict") strictfp
18  ret <4 x float> %ret
19}
20
21; Test an f32 addition that uses vector registers.
22define float @f2(<4 x float> %val1, <4 x float> %val2) strictfp {
23; CHECK-LABEL: f2:
24; CHECK: wfasb %f0, %v24, %v26
25; CHECK: br %r14
26  %scalar1 = extractelement <4 x float> %val1, i32 0
27  %scalar2 = extractelement <4 x float> %val2, i32 0
28  %ret = call float @llvm.experimental.constrained.fadd.f32(
29                        float %scalar1, float %scalar2,
30                        metadata !"round.dynamic",
31                        metadata !"fpexcept.strict") strictfp
32  ret float %ret
33}
34