1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4--- |
5  @arr = external dso_local local_unnamed_addr global [0 x i32], align 4
6
7  define dso_local arm_aapcs_vfpcc void @foo(i32 %i) {
8  entry:
9    %tobool.not11 = icmp eq i32 %i, 0
10    br i1 %tobool.not11, label %for.end5, label %vector.ph.preheader
11
12  vector.ph.preheader:                              ; preds = %entry
13    %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 3)
14    br label %vector.ph
15
16  vector.ph:                                        ; preds = %vector.ph.preheader, %vector.ph
17    %i.addr.012 = phi i32 [ %math, %vector.ph ], [ %i, %vector.ph.preheader ]
18    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> <i32 2, i32 2, i32 2, i32 2>, <4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*), i32 4, <4 x i1> %active.lane.mask)
19    %0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %i.addr.012, i32 1)
20    %math = extractvalue { i32, i1 } %0, 0
21    %ov = extractvalue { i32, i1 } %0, 1
22    br i1 %ov, label %for.end5, label %vector.ph
23
24  for.end5:                                         ; preds = %vector.ph, %entry
25    ret void
26  }
27
28  declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
29  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
30  declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
31
32...
33---
34name:            foo
35alignment:       8
36tracksRegLiveness: true
37registers:       []
38liveins:
39  - { reg: '$r0', virtual-reg: '' }
40frameInfo:
41  maxAlignment:    1
42  stackProtector:  ''
43  maxCallFrameSize: 0
44  cvBytesOfCalleeSavedRegisters: 0
45  localFrameSize:  0
46  savePoint:       ''
47  restorePoint:    ''
48fixedStack:      []
49stack:           []
50callSites:       []
51constants:
52  - id:              0
53    value:           '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
54    alignment:       8
55    isTargetSpecific: false
56machineFunctionInfo: {}
57body:             |
58  ; CHECK-LABEL: name: foo
59  ; CHECK: bb.0.entry:
60  ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
61  ; CHECK:   liveins: $r0
62  ; CHECK:   tCBZ $r0, %bb.3
63  ; CHECK: bb.1.vector.ph.preheader:
64  ; CHECK:   successors: %bb.2(0x80000000)
65  ; CHECK:   liveins: $r0
66  ; CHECK:   renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
67  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0
68  ; CHECK:   renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
69  ; CHECK:   $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
70  ; CHECK:   $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
71  ; CHECK:   renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg
72  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0
73  ; CHECK: bb.2.vector.ph:
74  ; CHECK:   successors: %bb.3(0x04000000), %bb.2(0x7c000000)
75  ; CHECK:   liveins: $vpr, $q0, $r0, $r1
76  ; CHECK:   renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
77  ; CHECK:   MVE_VPST 8, implicit $vpr
78  ; CHECK:   MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store 16 into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
79  ; CHECK:   tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
80  ; CHECK: bb.3.for.end5:
81  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
82  ; CHECK: bb.4 (align 8):
83  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
84  bb.0.entry:
85    successors: %bb.3(0x30000000), %bb.1(0x50000000)
86    liveins: $r0
87
88    tCBZ $r0, %bb.3
89
90  bb.1.vector.ph.preheader:
91    successors: %bb.2(0x80000000)
92    liveins: $r0
93
94    renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
95    renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0
96    renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
97    $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
98    $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
99    renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg
100    renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0
101
102  bb.2.vector.ph:
103    successors: %bb.3(0x04000000), %bb.2(0x7c000000)
104    liveins: $vpr, $q0, $r0, $r1
105
106    renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
107    MVE_VPST 8, implicit $vpr
108    MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store 16 into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
109    tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
110
111  bb.3.for.end5:
112    tBX_RET 14 /* CC::al */, $noreg
113
114  bb.4 (align 8):
115    CONSTPOOL_ENTRY 0, %const.0, 16
116
117...
118