1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - -verify-machineinstrs | FileCheck %s 3--- | 4 %struct.arm_biquad_casd_df1_inst_q31 = type { i32*, i32*, i32, i32 } 5 6 ; Function Attrs: optsize 7 define hidden void @arm_biquad_cascade_df1_q31(%struct.arm_biquad_casd_df1_inst_q31* nocapture readonly %arg, i32* nocapture readonly %arg1, i32* nocapture %arg2, i32 %arg3) #0 { 8 bb: 9 %i = bitcast %struct.arm_biquad_casd_df1_inst_q31* %arg to i32** 10 %i4 = load i32*, i32** %i, align 4 11 %i5 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 1 12 %i6 = load i32*, i32** %i5, align 4 13 %i7 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 2 14 %i8 = load i32, i32* %i7, align 4 15 %i9 = sub i32 31, %i8 16 %i10 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 3 17 %i11 = load i32, i32* %i10, align 4 18 br label %bb12 19 20 bb12: ; preds = %bb74, %bb 21 %i13 = phi i32* [ %i6, %bb ], [ %i18, %bb74 ] 22 %i14 = phi i32* [ %i4, %bb ], [ %i85, %bb74 ] 23 %i15 = phi i32* [ %arg1, %bb ], [ %arg2, %bb74 ] 24 %i16 = phi i32 [ %i11, %bb ], [ %i89, %bb74 ] 25 %i18 = getelementptr inbounds i32, i32* %i13, i32 5 26 %i19 = load i32, i32* %i14, align 4 27 %i20 = getelementptr inbounds i32, i32* %i14, i32 1 28 %i21 = load i32, i32* %i20, align 4 29 %i22 = getelementptr inbounds i32, i32* %i14, i32 2 30 %i23 = load i32, i32* %i22, align 4 31 %i24 = getelementptr inbounds i32, i32* %i14, i32 3 32 %i25 = load i32, i32* %i24, align 4 33 %i26 = call i1 @llvm.test.set.loop.iterations.i32(i32 %arg3) 34 br i1 %i26, label %bb27, label %bb74 35 36 bb27: ; preds = %bb12 37 %i28 = getelementptr inbounds i32, i32* %i13, i32 4 38 %i29 = load i32, i32* %i28, align 4 39 %i30 = getelementptr inbounds i32, i32* %i13, i32 3 40 %i31 = load i32, i32* %i30, align 4 41 %i32 = getelementptr inbounds i32, i32* %i13, i32 2 42 %i33 = load i32, i32* %i32, align 4 43 %i34 = getelementptr inbounds i32, i32* %i13, i32 1 44 %i35 = load i32, i32* %i34, align 4 45 %i36 = load i32, i32* %i13, align 4 46 br label %bb37 47 48 bb37: ; preds = %bb37, %bb27 49 %lsr.iv = phi i32 [ %lsr.iv.next, %bb37 ], [ %arg3, %bb27 ] 50 %i38 = phi i32* [ %i15, %bb27 ], [ %i51, %bb37 ] 51 %i39 = phi i32* [ %arg2, %bb27 ], [ %i69, %bb37 ] 52 %i40 = phi i32 [ %i25, %bb27 ], [ %i41, %bb37 ] 53 %i41 = phi i32 [ %i23, %bb27 ], [ %i68, %bb37 ] 54 %i42 = phi i32 [ %i21, %bb27 ], [ %i43, %bb37 ] 55 %i43 = phi i32 [ %i19, %bb27 ], [ %i52, %bb37 ] 56 %i45 = sext i32 %i29 to i64 57 %i46 = sext i32 %i31 to i64 58 %i47 = sext i32 %i33 to i64 59 %i48 = sext i32 %i35 to i64 60 %i49 = sext i32 %i36 to i64 61 %i50 = zext i32 %i9 to i64 62 %i51 = getelementptr inbounds i32, i32* %i38, i32 1 63 %i52 = load i32, i32* %i38, align 4 64 %i53 = sext i32 %i52 to i64 65 %i54 = mul nsw i64 %i53, %i49 66 %i55 = sext i32 %i43 to i64 67 %i56 = mul nsw i64 %i55, %i48 68 %i57 = sext i32 %i42 to i64 69 %i58 = mul nsw i64 %i57, %i47 70 %i59 = sext i32 %i41 to i64 71 %i60 = mul nsw i64 %i59, %i46 72 %i61 = sext i32 %i40 to i64 73 %i62 = mul nsw i64 %i61, %i45 74 %i63 = add i64 %i58, %i56 75 %i64 = add i64 %i63, %i60 76 %i65 = add i64 %i64, %i62 77 %i66 = add i64 %i65, %i54 78 %i67 = ashr i64 %i66, %i50 79 %i68 = trunc i64 %i67 to i32 80 %i69 = getelementptr inbounds i32, i32* %i39, i32 1 81 store i32 %i68, i32* %i39, align 4 82 %i70 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1) 83 %i71 = icmp ne i32 %i70, 0 84 %lsr.iv.next = add i32 %lsr.iv, -1 85 br i1 %i71, label %bb37, label %bb72 86 87 bb72: ; preds = %bb37 88 %i73 = trunc i64 %i67 to i32 89 br label %bb74 90 91 bb74: ; preds = %bb72, %bb12 92 %i75 = phi i32 [ %i19, %bb12 ], [ %i52, %bb72 ] 93 %i76 = phi i32 [ %i21, %bb12 ], [ %i43, %bb72 ] 94 %i77 = phi i32 [ %i23, %bb12 ], [ %i73, %bb72 ] 95 %i78 = phi i32 [ %i25, %bb12 ], [ %i41, %bb72 ] 96 store i32 %i75, i32* %i14, align 4 97 %i79 = bitcast i32* %i14 to i8* 98 %i80 = getelementptr inbounds i8, i8* %i79, i32 4 99 %i81 = bitcast i8* %i80 to i32* 100 store i32 %i76, i32* %i81, align 4 101 %i82 = bitcast i32* %i14 to i8* 102 %i83 = getelementptr inbounds i8, i8* %i82, i32 8 103 %i84 = bitcast i8* %i83 to i32* 104 store i32 %i77, i32* %i84, align 4 105 %i85 = getelementptr inbounds i32, i32* %i14, i32 4 106 %i86 = bitcast i32* %i14 to i8* 107 %i87 = getelementptr inbounds i8, i8* %i86, i32 12 108 %i88 = bitcast i8* %i87 to i32* 109 store i32 %i78, i32* %i88, align 4 110 %i89 = add i32 %i16, -1 111 %i90 = icmp eq i32 %i89, 0 112 br i1 %i90, label %bb91, label %bb12 113 114 bb91: ; preds = %bb74 115 ret void 116 } 117 118 declare i1 @llvm.test.set.loop.iterations.i32(i32) #1 119 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #1 120 121 attributes #0 = { optsize "target-cpu"="cortex-m55" } 122 attributes #1 = { noduplicate nounwind "target-cpu"="cortex-m55" } 123 124... 125--- 126name: arm_biquad_cascade_df1_q31 127alignment: 2 128tracksRegLiveness: true 129registers: [] 130liveins: 131 - { reg: '$r0', virtual-reg: '' } 132 - { reg: '$r1', virtual-reg: '' } 133 - { reg: '$r2', virtual-reg: '' } 134 - { reg: '$r3', virtual-reg: '' } 135frameInfo: 136 stackSize: 76 137 offsetAdjustment: 0 138 maxAlignment: 4 139 savePoint: '' 140 restorePoint: '' 141fixedStack: [] 142stack: 143 - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, 144 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 145 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 146 - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, 147 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 148 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 149 - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, 150 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 152 - { id: 3, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4, 153 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 155 - { id: 4, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4, 156 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 157 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 158 - { id: 5, name: '', type: spill-slot, offset: -60, size: 4, alignment: 4, 159 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 160 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 161 - { id: 6, name: '', type: spill-slot, offset: -64, size: 4, alignment: 4, 162 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 163 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 164 - { id: 7, name: '', type: spill-slot, offset: -68, size: 4, alignment: 4, 165 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 166 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 167 - { id: 8, name: '', type: spill-slot, offset: -72, size: 4, alignment: 4, 168 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 169 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 170 - { id: 9, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4, 171 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 172 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 173 - { id: 10, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 174 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 175 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 176 - { id: 11, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 177 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 178 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 179 - { id: 12, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 180 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 181 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 182 - { id: 13, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 183 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 184 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 185 - { id: 14, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 186 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 187 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 188 - { id: 15, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 189 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 190 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 191 - { id: 16, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 192 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 193 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 194 - { id: 17, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 195 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 196 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 197 - { id: 18, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 198 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 199 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 200callSites: [] 201constants: [] 202machineFunctionInfo: {} 203body: | 204 ; CHECK-LABEL: name: arm_biquad_cascade_df1_q31 205 ; CHECK: bb.0.bb: 206 ; CHECK: successors: %bb.1(0x80000000) 207 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 208 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 209 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 210 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 211 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 212 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 213 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 214 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 215 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 216 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 217 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 218 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 219 ; CHECK: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 220 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 76 221 ; CHECK: $r7, $r5 = t2LDRDi8 $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5) 222 ; CHECK: $r6, $r4 = t2LDRDi8 killed $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10) 223 ; CHECK: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 224 ; CHECK: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7) 225 ; CHECK: bb.1.bb12 (align 4): 226 ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) 227 ; CHECK: liveins: $r1, $r2, $r3, $r4, $r5, $r7 228 ; CHECK: $r9, $r8 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20) 229 ; CHECK: renamable $lr = nuw t2ADDri renamable $r5, 20, 14 /* CC::al */, $noreg, $noreg 230 ; CHECK: $r6, $r12 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24) 231 ; CHECK: t2CMPri renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 232 ; CHECK: tBcc %bb.5, 0 /* CC::eq */, killed $cpsr 233 ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg 234 ; CHECK: bb.2.bb27: 235 ; CHECK: successors: %bb.3(0x80000000) 236 ; CHECK: liveins: $lr, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12 237 ; CHECK: t2STRDi8 killed $lr, killed $r7, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5) 238 ; CHECK: renamable $r0 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13) 239 ; CHECK: renamable $r10 = t2LDRi12 renamable $r5, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28) 240 ; CHECK: tSTRspi killed renamable $r0, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 241 ; CHECK: renamable $r0 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34) 242 ; CHECK: tSTRspi killed renamable $r4, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.4) 243 ; CHECK: tSTRspi killed renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) 244 ; CHECK: renamable $r0 = tLDRi renamable $r5, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32) 245 ; CHECK: tSTRspi killed renamable $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) 246 ; CHECK: renamable $r0 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30) 247 ; CHECK: tSTRspi killed renamable $r0, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.3) 248 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 249 ; CHECK: renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9) 250 ; CHECK: bb.3.bb37 (align 4): 251 ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) 252 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r6, $r8, $r9, $r10, $r12 253 ; CHECK: renamable $r4 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) 254 ; CHECK: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 255 ; CHECK: $r5 = tMOVr $r9, 14 /* CC::al */, $noreg 256 ; CHECK: $lr = tMOVr $r0, 14 /* CC::al */, $noreg 257 ; CHECK: renamable $r6, renamable $r11 = t2SMULL killed $r9, killed renamable $r4, 14 /* CC::al */, $noreg 258 ; CHECK: renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) 259 ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg 260 ; CHECK: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38) 261 ; CHECK: dead renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr 262 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 263 ; CHECK: renamable $r4 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3) 264 ; CHECK: $r8 = tMOVr $r5, 14 /* CC::al */, $noreg 265 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 266 ; CHECK: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 267 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r12, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 268 ; CHECK: $r12 = tMOVr $r7, 14 /* CC::al */, $noreg 269 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 270 ; CHECK: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r3, 14 /* CC::al */, $noreg 271 ; CHECK: early-clobber renamable $r2 = t2STR_POST renamable $r6, killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39) 272 ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr 273 ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg 274 ; CHECK: bb.4.bb72: 275 ; CHECK: successors: %bb.5(0x80000000) 276 ; CHECK: liveins: $r5, $r6, $r7, $r9 277 ; CHECK: $r12 = tMOVr killed $r7, 14 /* CC::al */, $noreg 278 ; CHECK: $r7, $r4 = t2LDRDi8 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %stack.5), (load 4 from %stack.4) 279 ; CHECK: $lr = t2ADDri $sp, 4, 14 /* CC::al */, $noreg, $noreg 280 ; CHECK: $r8 = tMOVr killed $r5, 14 /* CC::al */, $noreg 281 ; CHECK: t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3, def $lr :: (load 4 from %stack.8), (load 4 from %stack.7), (load 4 from %stack.6) 282 ; CHECK: bb.5.bb74: 283 ; CHECK: successors: %bb.1(0x80000000) 284 ; CHECK: liveins: $lr, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r12 285 ; CHECK: t2STRDi8 killed $r9, killed $r8, $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81) 286 ; CHECK: t2STRDi8 killed $r6, killed $r12, $r7, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88) 287 ; CHECK: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg 288 ; CHECK: renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg 289 ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg 290 ; CHECK: $r1 = tMOVr $r2, 14 /* CC::al */, $noreg 291 ; CHECK: t2IT 0, 4, implicit-def $itstate 292 ; CHECK: $sp = frame-destroy tADDspi $sp, 10, 0 /* CC::eq */, $cpsr, implicit $itstate 293 ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit $sp, implicit killed $r4, implicit killed $r5, implicit killed $r7, implicit killed $itstate 294 ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg 295 bb.0.bb: 296 successors: %bb.1(0x80000000) 297 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 298 299 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 300 frame-setup CFI_INSTRUCTION def_cfa_offset 36 301 frame-setup CFI_INSTRUCTION offset $lr, -4 302 frame-setup CFI_INSTRUCTION offset $r11, -8 303 frame-setup CFI_INSTRUCTION offset $r10, -12 304 frame-setup CFI_INSTRUCTION offset $r9, -16 305 frame-setup CFI_INSTRUCTION offset $r8, -20 306 frame-setup CFI_INSTRUCTION offset $r7, -24 307 frame-setup CFI_INSTRUCTION offset $r6, -28 308 frame-setup CFI_INSTRUCTION offset $r5, -32 309 frame-setup CFI_INSTRUCTION offset $r4, -36 310 $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 311 frame-setup CFI_INSTRUCTION def_cfa_offset 76 312 $r7, $r5 = t2LDRDi8 $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5) 313 $r6, $r4 = t2LDRDi8 killed $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10) 314 renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 315 t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7) 316 317 bb.1.bb12 (align 4): 318 successors: %bb.2(0x40000000), %bb.5(0x40000000) 319 liveins: $r1, $r2, $r3, $r4, $r5, $r7 320 321 $r9, $r8 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20) 322 renamable $lr = nuw t2ADDri renamable $r5, 20, 14 /* CC::al */, $noreg, $noreg 323 $r6, $r12 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24) 324 t2WhileLoopStart renamable $r3, %bb.5, implicit-def dead $cpsr 325 tB %bb.2, 14 /* CC::al */, $noreg 326 327 bb.2.bb27: 328 successors: %bb.3(0x80000000) 329 liveins: $lr, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12 330 331 t2STRDi8 killed $lr, killed $r7, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5) 332 renamable $r0 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13) 333 renamable $r10 = t2LDRi12 renamable $r5, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28) 334 tSTRspi killed renamable $r0, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 335 renamable $r0 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34) 336 tSTRspi killed renamable $r4, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.4) 337 tSTRspi killed renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) 338 renamable $r0 = tLDRi renamable $r5, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32) 339 tSTRspi killed renamable $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) 340 renamable $r0 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30) 341 tSTRspi killed renamable $r0, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.3) 342 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 343 renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9) 344 345 bb.3.bb37 (align 4): 346 successors: %bb.3(0x7c000000), %bb.4(0x04000000) 347 liveins: $r0, $r1, $r2, $r3, $r6, $r8, $r9, $r10, $r12 348 349 renamable $r4 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) 350 $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 351 $r5 = tMOVr $r9, 14 /* CC::al */, $noreg 352 $lr = tMOVr $r0, 14 /* CC::al */, $noreg 353 renamable $r6, renamable $r11 = t2SMULL killed $r9, killed renamable $r4, 14 /* CC::al */, $noreg 354 renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) 355 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg 356 renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38) 357 renamable $lr = t2LoopDec killed renamable $lr, 1 358 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 359 renamable $r4 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3) 360 $r8 = tMOVr $r5, 14 /* CC::al */, $noreg 361 renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 362 renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 363 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r12, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 364 $r12 = tMOVr $r7, 14 /* CC::al */, $noreg 365 renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 366 early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r3, 14 /* CC::al */, $noreg 367 early-clobber renamable $r2 = t2STR_POST renamable $r6, killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39) 368 t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr 369 tB %bb.4, 14 /* CC::al */, $noreg 370 371 bb.4.bb72: 372 successors: %bb.5(0x80000000) 373 liveins: $r5, $r6, $r7, $r9 374 375 $r12 = tMOVr killed $r7, 14 /* CC::al */, $noreg 376 $r7, $r4 = t2LDRDi8 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %stack.5), (load 4 from %stack.4) 377 $lr = t2ADDri $sp, 4, 14 /* CC::al */, $noreg, $noreg 378 $r8 = tMOVr killed $r5, 14 /* CC::al */, $noreg 379 t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3, def $lr :: (load 4 from %stack.8), (load 4 from %stack.7), (load 4 from %stack.6) 380 381 bb.5.bb74: 382 successors: %bb.1(0x7c000000) 383 liveins: $lr, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r12 384 385 t2STRDi8 killed $r9, killed $r8, $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81) 386 t2STRDi8 killed $r6, killed $r12, $r7, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88) 387 renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg 388 renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg 389 $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg 390 $r1 = tMOVr $r2, 14 /* CC::al */, $noreg 391 t2IT 0, 4, implicit-def $itstate 392 $sp = frame-destroy tADDspi $sp, 10, 0 /* CC::eq */, $cpsr, implicit $itstate 393 $sp = frame-destroy t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit $sp, implicit killed $r4, implicit killed $r5, implicit killed $r7, implicit killed $itstate 394 tB %bb.1, 14 /* CC::al */, $noreg 395 396... 397