1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 %struct.arm_biquad_casd_df1_inst_q31 = type { i32*, i32*, i32, i32 } 6 7 ; Function Attrs: optsize 8 define hidden void @arm_biquad_cascade_df1_q31(%struct.arm_biquad_casd_df1_inst_q31* nocapture readonly %arg, i32* nocapture readonly %arg1, i32* nocapture %arg2, i32 %arg3) #0 { 9 bb: 10 %i = bitcast %struct.arm_biquad_casd_df1_inst_q31* %arg to i32** 11 %i4 = load i32*, i32** %i, align 4 12 %i5 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 1 13 %i6 = load i32*, i32** %i5, align 4 14 %i7 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 2 15 %i8 = load i32, i32* %i7, align 4 16 %i9 = sub i32 31, %i8 17 %i10 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 3 18 %i11 = load i32, i32* %i10, align 4 19 br label %bb12 20 21 bb12: ; preds = %bb74, %bb 22 %i13 = phi i32* [ %i6, %bb ], [ %i18, %bb74 ] 23 %i14 = phi i32* [ %i4, %bb ], [ %i85, %bb74 ] 24 %i15 = phi i32* [ %arg1, %bb ], [ %arg2, %bb74 ] 25 %i16 = phi i32 [ %i11, %bb ], [ %i89, %bb74 ] 26 %i18 = getelementptr inbounds i32, i32* %i13, i32 5 27 %i19 = load i32, i32* %i14, align 4 28 %i20 = getelementptr inbounds i32, i32* %i14, i32 1 29 %i21 = load i32, i32* %i20, align 4 30 %i22 = getelementptr inbounds i32, i32* %i14, i32 2 31 %i23 = load i32, i32* %i22, align 4 32 %i24 = getelementptr inbounds i32, i32* %i14, i32 3 33 %i25 = load i32, i32* %i24, align 4 34 %i26 = call i1 @llvm.test.set.loop.iterations.i32(i32 %arg3) 35 br i1 %i26, label %bb27, label %bb74 36 37 bb27: ; preds = %bb12 38 %i28 = getelementptr inbounds i32, i32* %i13, i32 4 39 %i29 = load i32, i32* %i28, align 4 40 %i30 = getelementptr inbounds i32, i32* %i13, i32 3 41 %i31 = load i32, i32* %i30, align 4 42 %i32 = getelementptr inbounds i32, i32* %i13, i32 2 43 %i33 = load i32, i32* %i32, align 4 44 %i34 = getelementptr inbounds i32, i32* %i13, i32 1 45 %i35 = load i32, i32* %i34, align 4 46 %i36 = load i32, i32* %i13, align 4 47 br label %bb37 48 49 bb37: ; preds = %bb37, %bb27 50 %lsr.iv = phi i32 [ %lsr.iv.next, %bb37 ], [ %arg3, %bb27 ] 51 %i38 = phi i32* [ %i15, %bb27 ], [ %i51, %bb37 ] 52 %i39 = phi i32* [ %arg2, %bb27 ], [ %i69, %bb37 ] 53 %i40 = phi i32 [ %i25, %bb27 ], [ %i41, %bb37 ] 54 %i41 = phi i32 [ %i23, %bb27 ], [ %i68, %bb37 ] 55 %i42 = phi i32 [ %i21, %bb27 ], [ %i43, %bb37 ] 56 %i43 = phi i32 [ %i19, %bb27 ], [ %i52, %bb37 ] 57 %i45 = sext i32 %i29 to i64 58 %i46 = sext i32 %i31 to i64 59 %i47 = sext i32 %i33 to i64 60 %i48 = sext i32 %i35 to i64 61 %i49 = sext i32 %i36 to i64 62 %i50 = zext i32 %i9 to i64 63 %i51 = getelementptr inbounds i32, i32* %i38, i32 1 64 %i52 = load i32, i32* %i38, align 4 65 %i53 = sext i32 %i52 to i64 66 %i54 = mul nsw i64 %i53, %i49 67 %i55 = sext i32 %i43 to i64 68 %i56 = mul nsw i64 %i55, %i48 69 %i57 = sext i32 %i42 to i64 70 %i58 = mul nsw i64 %i57, %i47 71 %i59 = sext i32 %i41 to i64 72 %i60 = mul nsw i64 %i59, %i46 73 %i61 = sext i32 %i40 to i64 74 %i62 = mul nsw i64 %i61, %i45 75 %i63 = add i64 %i58, %i56 76 %i64 = add i64 %i63, %i60 77 %i65 = add i64 %i64, %i62 78 %i66 = add i64 %i65, %i54 79 %i67 = ashr i64 %i66, %i50 80 %i68 = trunc i64 %i67 to i32 81 %i69 = getelementptr inbounds i32, i32* %i39, i32 1 82 store i32 %i68, i32* %i39, align 4 83 %i70 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1) 84 %i71 = icmp ne i32 %i70, 0 85 %lsr.iv.next = add i32 %lsr.iv, -1 86 br i1 %i71, label %bb37, label %bb72 87 88 bb72: ; preds = %bb37 89 %i73 = trunc i64 %i67 to i32 90 br label %bb74 91 92 bb74: ; preds = %bb72, %bb12 93 %i75 = phi i32 [ %i19, %bb12 ], [ %i52, %bb72 ] 94 %i76 = phi i32 [ %i21, %bb12 ], [ %i43, %bb72 ] 95 %i77 = phi i32 [ %i23, %bb12 ], [ %i73, %bb72 ] 96 %i78 = phi i32 [ %i25, %bb12 ], [ %i41, %bb72 ] 97 store i32 %i75, i32* %i14, align 4 98 %i79 = bitcast i32* %i14 to i8* 99 %i80 = getelementptr inbounds i8, i8* %i79, i32 4 100 %i81 = bitcast i8* %i80 to i32* 101 store i32 %i76, i32* %i81, align 4 102 %i82 = bitcast i32* %i14 to i8* 103 %i83 = getelementptr inbounds i8, i8* %i82, i32 8 104 %i84 = bitcast i8* %i83 to i32* 105 store i32 %i77, i32* %i84, align 4 106 %i85 = getelementptr inbounds i32, i32* %i14, i32 4 107 %i86 = bitcast i32* %i14 to i8* 108 %i87 = getelementptr inbounds i8, i8* %i86, i32 12 109 %i88 = bitcast i8* %i87 to i32* 110 store i32 %i78, i32* %i88, align 4 111 %i89 = add i32 %i16, -1 112 %i90 = icmp eq i32 %i89, 0 113 br i1 %i90, label %bb91, label %bb12 114 115 bb91: ; preds = %bb74 116 ret void 117 } 118 119 ; Function Attrs: noduplicate nounwind 120 declare i1 @llvm.test.set.loop.iterations.i32(i32) #1 121 122 ; Function Attrs: noduplicate nounwind 123 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #1 124 125 attributes #0 = { optsize "target-cpu"="cortex-m55" } 126 attributes #1 = { noduplicate nounwind "target-cpu"="cortex-m55" } 127 128... 129--- 130name: arm_biquad_cascade_df1_q31 131alignment: 2 132tracksRegLiveness: true 133registers: [] 134liveins: 135 - { reg: '$r0', virtual-reg: '' } 136 - { reg: '$r1', virtual-reg: '' } 137 - { reg: '$r2', virtual-reg: '' } 138 - { reg: '$r3', virtual-reg: '' } 139frameInfo: 140 stackSize: 76 141 offsetAdjustment: 0 142 maxAlignment: 4 143 localFrameSize: 0 144 savePoint: '' 145 restorePoint: '' 146fixedStack: [] 147stack: 148 - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, 149 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 150 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 151 - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, 152 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 153 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 154 - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, 155 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 156 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 157 - { id: 3, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4, 158 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 159 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 160 - { id: 4, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4, 161 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 162 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 163 - { id: 5, name: '', type: spill-slot, offset: -60, size: 4, alignment: 4, 164 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 165 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 166 - { id: 6, name: '', type: spill-slot, offset: -64, size: 4, alignment: 4, 167 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 168 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 169 - { id: 7, name: '', type: spill-slot, offset: -68, size: 4, alignment: 4, 170 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 171 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 172 - { id: 8, name: '', type: spill-slot, offset: -72, size: 4, alignment: 4, 173 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 174 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 175 - { id: 9, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4, 176 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 177 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 178 - { id: 10, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 179 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 180 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 181 - { id: 11, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 182 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 183 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 184 - { id: 12, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 185 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 186 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 187 - { id: 13, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 188 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 189 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 190 - { id: 14, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 191 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 192 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 193 - { id: 15, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 194 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 195 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 196 - { id: 16, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 197 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 198 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 199 - { id: 17, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 200 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 201 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 202 - { id: 18, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 203 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 204 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 205callSites: [] 206constants: [] 207machineFunctionInfo: {} 208body: | 209 ; CHECK-LABEL: name: arm_biquad_cascade_df1_q31 210 ; CHECK: bb.0.bb: 211 ; CHECK: successors: %bb.1(0x80000000) 212 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 213 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 214 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 215 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 216 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 217 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 218 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 219 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 220 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 221 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 222 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 223 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 224 ; CHECK: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 225 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 76 226 ; CHECK: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10) 227 ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg 228 ; CHECK: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5) 229 ; CHECK: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 230 ; CHECK: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7) 231 ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 232 ; CHECK: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9) 233 ; CHECK: bb.1.bb12 (align 4): 234 ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000) 235 ; CHECK: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12 236 ; CHECK: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20) 237 ; CHECK: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24) 238 ; CHECK: dead $lr = t2WLS renamable $r8, %bb.5 239 ; CHECK: bb.2.bb27: 240 ; CHECK: successors: %bb.3(0x80000000) 241 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12 242 ; CHECK: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5) 243 ; CHECK: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13) 244 ; CHECK: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 245 ; CHECK: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34) 246 ; CHECK: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) 247 ; CHECK: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32) 248 ; CHECK: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) 249 ; CHECK: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30) 250 ; CHECK: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store 4 into %stack.4), (store 4 into %stack.3) 251 ; CHECK: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28) 252 ; CHECK: bb.3.bb37 (align 4): 253 ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) 254 ; CHECK: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12 255 ; CHECK: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 256 ; CHECK: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) 257 ; CHECK: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) 258 ; CHECK: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg 259 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 260 ; CHECK: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3) 261 ; CHECK: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg 262 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 263 ; CHECK: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38) 264 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 265 ; CHECK: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 266 ; CHECK: $lr = tMOVr $r8, 14 /* CC::al */, $noreg 267 ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 268 ; CHECK: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg 269 ; CHECK: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39) 270 ; CHECK: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 271 ; CHECK: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg 272 ; CHECK: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg 273 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.3 274 ; CHECK: bb.4.bb72: 275 ; CHECK: successors: %bb.5(0x80000000) 276 ; CHECK: liveins: $r2, $r5, $r6, $r7, $r9 277 ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg 278 ; CHECK: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 279 ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg 280 ; CHECK: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.8), (load 4 from %stack.7) 281 ; CHECK: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load 4 from %stack.6), (load 4 from %stack.5), (load 4 from %stack.4) 282 ; CHECK: bb.5.bb74: 283 ; CHECK: successors: %bb.6(0x04000000), %bb.1(0x7c000000) 284 ; CHECK: liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 285 ; CHECK: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg 286 ; CHECK: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81) 287 ; CHECK: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88) 288 ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg 289 ; CHECK: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg 290 ; CHECK: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg 291 ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr 292 ; CHECK: bb.6.bb91: 293 ; CHECK: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg 294 ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc 295 bb.0.bb: 296 successors: %bb.1(0x80000000) 297 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 298 299 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 300 frame-setup CFI_INSTRUCTION def_cfa_offset 36 301 frame-setup CFI_INSTRUCTION offset $lr, -4 302 frame-setup CFI_INSTRUCTION offset $r11, -8 303 frame-setup CFI_INSTRUCTION offset $r10, -12 304 frame-setup CFI_INSTRUCTION offset $r9, -16 305 frame-setup CFI_INSTRUCTION offset $r8, -20 306 frame-setup CFI_INSTRUCTION offset $r7, -24 307 frame-setup CFI_INSTRUCTION offset $r6, -28 308 frame-setup CFI_INSTRUCTION offset $r5, -32 309 frame-setup CFI_INSTRUCTION offset $r4, -36 310 $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 311 frame-setup CFI_INSTRUCTION def_cfa_offset 76 312 $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10) 313 $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg 314 $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5) 315 renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 316 t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7) 317 $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 318 renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9) 319 320 bb.1.bb12 (align 4): 321 successors: %bb.2(0x40000000), %bb.5(0x40000000) 322 liveins: $r1, $r3, $r5, $r7, $r8, $r12, $r2 323 324 $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20) 325 $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24) 326 t2WhileLoopStart renamable $r8, %bb.5, implicit-def dead $cpsr 327 tB %bb.2, 14 /* CC::al */, $noreg 328 329 bb.2.bb27: 330 successors: %bb.3(0x80000000) 331 liveins: $r0, $r1, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 332 333 t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5) 334 renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13) 335 tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 336 renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34) 337 tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) 338 renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32) 339 tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) 340 renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30) 341 t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store 4 into %stack.4), (store 4 into %stack.3) 342 renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28) 343 344 bb.3.bb37 (align 4): 345 successors: %bb.3(0x7c000000), %bb.4(0x04000000) 346 liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12 347 348 $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 349 renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) 350 renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) 351 renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg 352 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 353 renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3) 354 $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg 355 renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 356 renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38) 357 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 358 renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 359 $lr = tMOVr $r8, 14 /* CC::al */, $noreg 360 renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 361 early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg 362 early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39) 363 renamable $lr = t2LoopDec killed renamable $lr, 1 364 renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 365 $r0 = tMOVr $r7, 14 /* CC::al */, $noreg 366 $r4 = tMOVr $r5, 14 /* CC::al */, $noreg 367 t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr 368 tB %bb.4, 14 /* CC::al */, $noreg 369 370 bb.4.bb72: 371 successors: %bb.5(0x80000000) 372 liveins: $r5, $r6, $r7, $r9, $r2 373 374 $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg 375 $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 376 $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg 377 $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.8), (load 4 from %stack.7) 378 tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load 4 from %stack.6), (load 4 from %stack.5), (load 4 from %stack.4) 379 380 bb.5.bb74: 381 successors: %bb.6(0x04000000), %bb.1(0x7c000000) 382 liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 383 384 renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg 385 t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81) 386 t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88) 387 renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg 388 renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg 389 $r1 = tMOVr $r12, 14 /* CC::al */, $noreg 390 tBcc %bb.1, 1 /* CC::ne */, killed $cpsr 391 392 bb.6.bb91: 393 $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg 394 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc 395 396... 397