1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3# 4--- | 5 @mask = external global i16 6 define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i32* noalias nocapture readonly %arg3) local_unnamed_addr #0 { 7 bb: 8 %tmp = icmp eq i32 %arg2, 0 9 %tmp1 = add i32 %arg2, 3 10 %tmp2 = lshr i32 %tmp1, 2 11 %tmp3 = shl nuw i32 %tmp2, 2 12 %tmp4 = add i32 %tmp3, -4 13 %tmp5 = lshr i32 %tmp4, 2 14 %tmp6 = add nuw nsw i32 %tmp5, 1 15 %mask.gep9 = bitcast i16* @mask to i16* 16 %mask.load = load i16, i16* %mask.gep9 17 %conv.mask = zext i16 %mask.load to i32 18 %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask) 19 br i1 %tmp, label %bb27, label %bb3 20 21 bb3: ; preds = %bb 22 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6) 23 %scevgep1 = getelementptr i32, i32* %arg3, i32 -4 24 br label %bb9 25 26 bb9: ; preds = %bb9, %bb3 27 %lsr.iv4 = phi i32* [ %scevgep6, %bb9 ], [ %scevgep1, %bb3 ] 28 %lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ] 29 %lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ] 30 %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ] 31 %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ] 32 %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>* 33 %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>* 34 %lsr.iv47 = bitcast i32* %lsr.iv4 to <4 x i32>* 35 %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8) 36 %and = and <4 x i1> %vctp, %invariant.mask 37 %tmp11 = sub i32 %tmp8, 4 38 %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef) 39 %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef) 40 %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17 41 %scevgep2 = getelementptr <4 x i32>, <4 x i32>* %lsr.iv47, i32 1 42 %load.limits = load <4 x i32>, <4 x i32>* %scevgep2 43 %0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0 44 %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer 45 %bad.icmp = icmp ule <4 x i32> %load.limits, %1 46 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %bad.icmp) 47 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1) 48 %tmp13 = icmp ne i32 %tmp12, 0 49 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 50 %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4 51 %scevgep6 = getelementptr i32, i32* %lsr.iv4, i32 4 52 br i1 %tmp13, label %bb9, label %bb27 53 54 bb27: ; preds = %bb9, %bb 55 ret void 56 } 57 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 58 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 59 declare i32 @llvm.start.loop.iterations.i32(i32) 60 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 61 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 62 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 63 64... 65--- 66name: test 67alignment: 2 68exposesReturnsTwice: false 69legalized: false 70regBankSelected: false 71selected: false 72failedISel: false 73tracksRegLiveness: true 74hasWinCFI: false 75registers: [] 76liveins: 77 - { reg: '$r0', virtual-reg: '' } 78 - { reg: '$r1', virtual-reg: '' } 79 - { reg: '$r2', virtual-reg: '' } 80 - { reg: '$r3', virtual-reg: '' } 81frameInfo: 82 isFrameAddressTaken: false 83 isReturnAddressTaken: false 84 hasStackMap: false 85 hasPatchPoint: false 86 stackSize: 20 87 offsetAdjustment: 0 88 maxAlignment: 4 89 adjustsStack: false 90 hasCalls: false 91 stackProtector: '' 92 maxCallFrameSize: 0 93 cvBytesOfCalleeSavedRegisters: 0 94 hasOpaqueSPAdjustment: false 95 hasVAStart: false 96 hasMustTailInVarArgFunc: false 97 localFrameSize: 0 98 savePoint: '' 99 restorePoint: '' 100fixedStack: [] 101stack: 102 - { id: 0, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 103 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 104 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 105 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 106 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 107 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 108 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 109 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 110 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 111 - { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 112 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 113 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 114 - { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 115 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 116 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 117callSites: [] 118constants: [] 119machineFunctionInfo: {} 120body: | 121 ; CHECK-LABEL: name: test 122 ; CHECK: bb.0.bb: 123 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 124 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 125 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 126 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 127 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 128 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 129 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 130 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 131 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 132 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 133 ; CHECK: tCBZ $r2, %bb.3 134 ; CHECK: bb.1.bb3: 135 ; CHECK: successors: %bb.2(0x80000000) 136 ; CHECK: liveins: $r0, $r1, $r2, $r3 137 ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg 138 ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 139 ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg 140 ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg 141 ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) 142 ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg 143 ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 144 ; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg 145 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 146 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg 147 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 148 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 149 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 150 ; CHECK: $lr = t2DLS killed renamable $lr 151 ; CHECK: bb.2.bb9: 152 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 153 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 154 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 155 ; CHECK: MVE_VPST 2, implicit $vpr 156 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 157 ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) 158 ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) 159 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 160 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 161 ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) 162 ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr 163 ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) 164 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 165 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 166 ; CHECK: bb.3.bb27: 167 ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 168 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc 169 bb.0.bb: 170 successors: %bb.3(0x30000000), %bb.1(0x50000000) 171 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr 172 173 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 174 frame-setup CFI_INSTRUCTION def_cfa_offset 16 175 frame-setup CFI_INSTRUCTION offset $lr, -4 176 frame-setup CFI_INSTRUCTION offset $r7, -8 177 frame-setup CFI_INSTRUCTION offset $r5, -12 178 frame-setup CFI_INSTRUCTION offset $r4, -16 179 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 180 frame-setup CFI_INSTRUCTION def_cfa_offset 20 181 tCBZ $r2, %bb.3 182 183 bb.1.bb3: 184 successors: %bb.2(0x80000000) 185 liveins: $r0, $r1, $r2, $r3 186 187 $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg 188 renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg 189 $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg 190 renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg 191 renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) 192 renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg 193 renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg 194 $vpr = VMSR_P0 $r5, 14, $noreg 195 renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg 196 renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg 197 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) 198 renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 199 $r3 = tMOVr $r0, 14, $noreg 200 $lr = t2DoLoopStart renamable $lr 201 202 bb.2.bb9: 203 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 204 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 205 206 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) 207 MVE_VPST 2, implicit $vpr 208 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 209 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) 210 renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) 211 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 212 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 213 renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) 214 MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr 215 MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) 216 renamable $lr = t2LoopDec killed renamable $lr, 1 217 $r0 = tMOVr $r3, 14, $noreg 218 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 219 tB %bb.3, 14, $noreg 220 221 bb.3.bb27: 222 $sp = tADDspi $sp, 1, 14, $noreg 223 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc 224 225... 226