1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
3
4--- |
5  define hidden arm_aapcs_vfpcc void @dont_ignore_vctp(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
6  entry:
7    %mul = shl i32 %blockSize, 1
8    %0 = add i32 %mul, 3
9    %1 = icmp slt i32 %mul, 4
10    %smin = select i1 %1, i32 %mul, i32 4
11    %2 = sub i32 %0, %smin
12    %3 = lshr i32 %2, 2
13    %4 = add nuw nsw i32 %3, 1
14    %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)
15    br label %do.body
16
17  do.body:                                          ; preds = %do.body, %entry
18    %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
19    %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
20    %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
21    %5 = phi i32 [ %start, %entry ], [ %9, %do.body ]
22    %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
23    %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
24    %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
25    %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
26    %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
27    tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
28    %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
29    %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
30    %sub = add nsw i32 %blkCnt.0, -4
31    %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
32    %10 = icmp ne i32 %9, 0
33    br i1 %10, label %do.body, label %do.end
34
35  do.end:                                           ; preds = %do.body
36    ret void
37  }
38  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
39  declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
40  declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
41  declare i32 @llvm.start.loop.iterations.i32(i32)
42  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
43
44...
45---
46name:            dont_ignore_vctp
47alignment:       16
48exposesReturnsTwice: false
49legalized:       false
50regBankSelected: false
51selected:        false
52failedISel:      false
53tracksRegLiveness: true
54hasWinCFI:       false
55registers:       []
56liveins:
57  - { reg: '$r0', virtual-reg: '' }
58  - { reg: '$r1', virtual-reg: '' }
59  - { reg: '$r2', virtual-reg: '' }
60frameInfo:
61  isFrameAddressTaken: false
62  isReturnAddressTaken: false
63  hasStackMap:     false
64  hasPatchPoint:   false
65  stackSize:       8
66  offsetAdjustment: 0
67  maxAlignment:    4
68  adjustsStack:    false
69  hasCalls:        false
70  stackProtector:  ''
71  maxCallFrameSize: 0
72  cvBytesOfCalleeSavedRegisters: 0
73  hasOpaqueSPAdjustment: false
74  hasVAStart:      false
75  hasMustTailInVarArgFunc: false
76  localFrameSize:  0
77  savePoint:       ''
78  restorePoint:    ''
79fixedStack:      []
80stack:
81  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
82      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
83      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
84  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
85      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
86      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
87callSites:       []
88constants:
89  - id:              0
90    value:           '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
91    alignment:       16
92    isTargetSpecific: false
93machineFunctionInfo: {}
94body:             |
95  ; CHECK-LABEL: name: dont_ignore_vctp
96  ; CHECK: bb.0.entry:
97  ; CHECK:   successors: %bb.1(0x80000000)
98  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
99  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
100  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
101  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
102  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
103  ; CHECK:   renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
104  ; CHECK:   renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
105  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
106  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
107  ; CHECK: bb.1.do.body (align 4):
108  ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
109  ; CHECK:   liveins: $lr, $q0, $r0, $r1
110  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
111  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
112  ; CHECK:   MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
113  ; CHECK:   renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
114  ; CHECK:   renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
115  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
116  ; CHECK: bb.2.do.end:
117  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
118  ; CHECK: bb.3 (align 16):
119  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
120  bb.0.entry:
121    successors: %bb.1(0x80000000)
122    liveins: $r0, $r1, $r2, $r7, $lr
123
124    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
125    frame-setup CFI_INSTRUCTION def_cfa_offset 8
126    frame-setup CFI_INSTRUCTION offset $lr, -4
127    frame-setup CFI_INSTRUCTION offset $r7, -8
128    renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
129    renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
130    tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
131    t2IT 11, 8, implicit-def $itstate
132    $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
133    renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
134    renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
135    renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
136    renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
137    renamable $r2 = tLEApcrel %const.0, 14, $noreg
138    renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
139    $lr = t2DoLoopStart renamable $lr
140
141  bb.1.do.body (align 4):
142    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
143    liveins: $lr, $q0, $r0, $r1, $r3
144
145    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
146    MVE_VPST 2, implicit $vpr
147    renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
148    renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
149    MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
150    renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
151    renamable $lr = t2LoopDec killed renamable $lr, 1
152    renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
153    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
154    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
155    tB %bb.2, 14, $noreg
156
157  bb.2.do.end:
158    tPOP_RET 14, $noreg, def $r7, def $pc
159
160  bb.3 (align 16):
161    CONSTPOOL_ENTRY 0, %const.0, 16
162
163...
164