1# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 2 3# This test was originally hitting problems with empty blocks. That went away 4# but the underlying problem (empty blocks causing iterator issues) still remains. 5# The test adds an extra empty block to one of the loops to test this. 6 7# CHECK: LETP 8 9--- | 10 %struct.DCT_InstanceTypeDef = type { float*, i32, i32 } 11 12 ; Function Attrs: nofree nounwind 13 define hidden arm_aapcs_vfpcc void @test(%struct.DCT_InstanceTypeDef* nocapture readonly %S, float* %pIn, float* nocapture %pOut) { 14 entry: 15 %NumInputs = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 2 16 %0 = load i32, i32* %NumInputs, align 4 17 %NumFilters = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 1 18 %1 = load i32, i32* %NumFilters, align 4 19 %pDCTCoefs34 = bitcast %struct.DCT_InstanceTypeDef* %S to float** 20 %2 = load float*, float** %pDCTCoefs34, align 4 21 %3 = add i32 %0, 3 22 %4 = icmp slt i32 %0, 4 23 %smin36 = select i1 %4, i32 %0, i32 4 24 %5 = sub i32 %3, %smin36 25 %6 = lshr i32 %5, 2 26 %7 = add nuw nsw i32 %6, 1 27 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %7) 28 br label %do.body 29 30 do.body: ; preds = %do.body, %entry 31 %count.0 = phi i32 [ %0, %entry ], [ %12, %do.body ] 32 %pInT.0 = phi float* [ %pIn, %entry ], [ %add.ptr, %do.body ] 33 %sumVec.0 = phi <4 x float> [ zeroinitializer, %entry ], [ %11, %do.body ] 34 %8 = phi i32 [ %start1, %entry ], [ %13, %do.body ] 35 %pInT.033 = bitcast float* %pInT.0 to <4 x float>* 36 %9 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %count.0) 37 %10 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pInT.033, i32 4, <4 x i1> %9, <4 x float> zeroinitializer) 38 %11 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0, <4 x float> %10, <4 x i1> %9, <4 x float> undef) 39 %add.ptr = getelementptr inbounds float, float* %pInT.0, i32 4 40 %12 = add i32 %count.0, -4 41 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %8, i32 1) 42 %14 = icmp ne i32 %13, 0 43 br i1 %14, label %do.body, label %do.end 44 45 do.end: ; preds = %do.body 46 %15 = extractelement <4 x float> %11, i32 0 47 %16 = extractelement <4 x float> %11, i32 1 48 %add = fadd fast float %15, %16 49 %17 = extractelement <4 x float> %11, i32 2 50 %add1 = fadd fast float %add, %17 51 %18 = extractelement <4 x float> %11, i32 3 52 %add2 = fadd fast float %add1, %18 53 %19 = load float, float* %2, align 4 54 %mul = fmul fast float %19, %add2 55 store float %mul, float* %pOut, align 4 56 %sub4 = add i32 %1, -4 57 %cmp5201 = icmp ugt i32 %sub4, 1 58 br i1 %cmp5201, label %for.body.lr.ph, label %for.cond54.preheader 59 60 for.body.lr.ph: ; preds = %do.end 61 %scevgep = getelementptr float, float* %pIn, i32 4 62 %20 = add i32 %0, 4 63 %scevgep5 = getelementptr float, float* %2, i32 %20 64 %21 = shl i32 %0, 4 65 %22 = shl i32 %0, 1 66 %23 = add i32 %22, 4 67 %scevgep12 = getelementptr float, float* %2, i32 %23 68 %24 = mul i32 %0, 3 69 %25 = add i32 %24, 4 70 %scevgep19 = getelementptr float, float* %2, i32 %25 71 %26 = shl i32 %0, 2 72 %27 = add i32 %26, 4 73 %scevgep26 = getelementptr float, float* %2, i32 %27 74 %28 = add i32 %0, -1 75 %29 = add i32 %0, -4 76 %30 = icmp slt i32 %29, 4 77 %smin35 = select i1 %30, i32 %29, i32 4 78 %31 = sub i32 %28, %smin35 79 %32 = lshr i32 %31, 2 80 %33 = add nuw nsw i32 %32, 1 81 br label %for.body 82 83 for.cond54.preheader: ; preds = %do.end33, %do.end 84 %k.0.lcssa = phi i32 [ 1, %do.end ], [ %add53, %do.end33 ] 85 %cmp55199 = icmp ult i32 %k.0.lcssa, %1 86 br i1 %cmp55199, label %for.body56.preheader, label %for.end72 87 88 for.body56.preheader: ; preds = %for.cond54.preheader 89 %34 = add i32 %0, 3 90 %35 = icmp slt i32 %0, 4 91 %smin = select i1 %35, i32 %0, i32 4 92 %36 = sub i32 %34, %smin 93 %37 = lshr i32 %36, 2 94 %38 = add nuw nsw i32 %37, 1 95 br label %for.body56 96 97 for.body: ; preds = %do.end33, %for.body.lr.ph 98 %lsr.iv27 = phi float* [ %88, %do.end33 ], [ %scevgep26, %for.body.lr.ph ] 99 %lsr.iv20 = phi float* [ %87, %do.end33 ], [ %scevgep19, %for.body.lr.ph ] 100 %lsr.iv13 = phi float* [ %86, %do.end33 ], [ %scevgep12, %for.body.lr.ph ] 101 %lsr.iv6 = phi float* [ %85, %do.end33 ], [ %scevgep5, %for.body.lr.ph ] 102 %k.0202 = phi i32 [ 1, %for.body.lr.ph ], [ %add53, %do.end33 ] 103 %39 = bitcast float* %pIn to <4 x float>* 104 %mul7 = mul i32 %k.0202, %0 105 %arrayidx8 = getelementptr inbounds float, float* %2, i32 %mul7 106 %add9 = add nuw nsw i32 %k.0202, 1 107 %mul10 = mul i32 %add9, %0 108 %arrayidx11 = getelementptr inbounds float, float* %2, i32 %mul10 109 %add12 = add nuw nsw i32 %k.0202, 2 110 %mul13 = mul i32 %add12, %0 111 %arrayidx14 = getelementptr inbounds float, float* %2, i32 %mul13 112 %add15 = add i32 %k.0202, 3 113 %mul16 = mul i32 %add15, %0 114 %arrayidx17 = getelementptr inbounds float, float* %2, i32 %mul16 115 %40 = load <4 x float>, <4 x float>* %39, align 4 116 %41 = bitcast float* %arrayidx8 to <4 x float>* 117 %42 = load <4 x float>, <4 x float>* %41, align 4 118 %43 = fmul fast <4 x float> %42, %40 119 %44 = bitcast float* %arrayidx11 to <4 x float>* 120 %45 = load <4 x float>, <4 x float>* %44, align 4 121 %46 = fmul fast <4 x float> %45, %40 122 %47 = bitcast float* %arrayidx14 to <4 x float>* 123 %48 = load <4 x float>, <4 x float>* %47, align 4 124 %49 = fmul fast <4 x float> %48, %40 125 %50 = bitcast float* %arrayidx17 to <4 x float>* 126 %51 = load <4 x float>, <4 x float>* %50, align 4 127 %52 = fmul fast <4 x float> %51, %40 128 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %33) 129 br label %do.body24 130 131 do.body24: ; preds = %do.body24, %for.body 132 %lsr.iv30 = phi float* [ %scevgep31, %do.body24 ], [ %lsr.iv27, %for.body ] 133 %lsr.iv23 = phi float* [ %scevgep24, %do.body24 ], [ %lsr.iv20, %for.body ] 134 %lsr.iv16 = phi float* [ %scevgep17, %do.body24 ], [ %lsr.iv13, %for.body ] 135 %lsr.iv9 = phi float* [ %scevgep10, %do.body24 ], [ %lsr.iv6, %for.body ] 136 %lsr.iv = phi float* [ %scevgep3, %do.body24 ], [ %scevgep, %for.body ] 137 %sumVec0.0 = phi <4 x float> [ %43, %for.body ], [ %56, %do.body24 ] 138 %sumVec1.0 = phi <4 x float> [ %46, %for.body ], [ %58, %do.body24 ] 139 %sumVec2.0 = phi <4 x float> [ %49, %for.body ], [ %60, %do.body24 ] 140 %sumVec3.0 = phi <4 x float> [ %52, %for.body ], [ %62, %do.body24 ] 141 %53 = phi i32 [ %start2, %for.body ], [ %63, %do.body24 ] 142 %lsr.iv4 = bitcast float* %lsr.iv to <4 x float>* 143 %lsr.iv911 = bitcast float* %lsr.iv9 to <4 x float>* 144 %lsr.iv1618 = bitcast float* %lsr.iv16 to <4 x float>* 145 %lsr.iv2325 = bitcast float* %lsr.iv23 to <4 x float>* 146 %lsr.iv3032 = bitcast float* %lsr.iv30 to <4 x float>* 147 %54 = load <4 x float>, <4 x float>* %lsr.iv4, align 4 148 %55 = load <4 x float>, <4 x float>* %lsr.iv911, align 4 149 %56 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %55, <4 x float> %sumVec0.0) 150 %57 = load <4 x float>, <4 x float>* %lsr.iv1618, align 4 151 %58 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %57, <4 x float> %sumVec1.0) 152 %59 = load <4 x float>, <4 x float>* %lsr.iv2325, align 4 153 %60 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %59, <4 x float> %sumVec2.0) 154 %61 = load <4 x float>, <4 x float>* %lsr.iv3032, align 4 155 %62 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %61, <4 x float> %sumVec3.0) 156 %scevgep3 = getelementptr float, float* %lsr.iv, i32 4 157 %scevgep10 = getelementptr float, float* %lsr.iv9, i32 4 158 %scevgep17 = getelementptr float, float* %lsr.iv16, i32 4 159 %scevgep24 = getelementptr float, float* %lsr.iv23, i32 4 160 %scevgep31 = getelementptr float, float* %lsr.iv30, i32 4 161 %63 = call i32 @llvm.loop.decrement.reg.i32(i32 %53, i32 1) 162 %64 = icmp ne i32 %63, 0 163 br i1 %64, label %do.body24, label %do.end33 164 165 do.end33: ; preds = %do.body24 166 %65 = bitcast float* %lsr.iv27 to i1* 167 %66 = bitcast float* %lsr.iv20 to i1* 168 %67 = bitcast float* %lsr.iv13 to i1* 169 %68 = bitcast float* %lsr.iv6 to i1* 170 %69 = extractelement <4 x float> %56, i32 0 171 %70 = extractelement <4 x float> %56, i32 1 172 %add34 = fadd fast float %69, %70 173 %71 = extractelement <4 x float> %56, i32 2 174 %add35 = fadd fast float %add34, %71 175 %72 = extractelement <4 x float> %56, i32 3 176 %add36 = fadd fast float %add35, %72 177 %arrayidx37 = getelementptr inbounds float, float* %pOut, i32 %k.0202 178 store float %add36, float* %arrayidx37, align 4 179 %73 = extractelement <4 x float> %58, i32 0 180 %74 = extractelement <4 x float> %58, i32 1 181 %add38 = fadd fast float %73, %74 182 %75 = extractelement <4 x float> %58, i32 2 183 %add39 = fadd fast float %add38, %75 184 %76 = extractelement <4 x float> %58, i32 3 185 %add40 = fadd fast float %add39, %76 186 %arrayidx42 = getelementptr inbounds float, float* %pOut, i32 %add9 187 store float %add40, float* %arrayidx42, align 4 188 %77 = extractelement <4 x float> %60, i32 0 189 %78 = extractelement <4 x float> %60, i32 1 190 %add43 = fadd fast float %77, %78 191 %79 = extractelement <4 x float> %60, i32 2 192 %add44 = fadd fast float %add43, %79 193 %80 = extractelement <4 x float> %60, i32 3 194 %add45 = fadd fast float %add44, %80 195 %arrayidx47 = getelementptr inbounds float, float* %pOut, i32 %add12 196 store float %add45, float* %arrayidx47, align 4 197 %81 = extractelement <4 x float> %62, i32 0 198 %82 = extractelement <4 x float> %62, i32 1 199 %add48 = fadd fast float %81, %82 200 %83 = extractelement <4 x float> %62, i32 2 201 %add49 = fadd fast float %add48, %83 202 %84 = extractelement <4 x float> %62, i32 3 203 %add50 = fadd fast float %add49, %84 204 %arrayidx52 = getelementptr inbounds float, float* %pOut, i32 %add15 205 store float %add50, float* %arrayidx52, align 4 206 %add53 = add i32 %k.0202, 4 207 %scevgep8 = getelementptr i1, i1* %68, i32 %21 208 %85 = bitcast i1* %scevgep8 to float* 209 %scevgep15 = getelementptr i1, i1* %67, i32 %21 210 %86 = bitcast i1* %scevgep15 to float* 211 %scevgep22 = getelementptr i1, i1* %66, i32 %21 212 %87 = bitcast i1* %scevgep22 to float* 213 %scevgep29 = getelementptr i1, i1* %65, i32 %21 214 %88 = bitcast i1* %scevgep29 to float* 215 %cmp5 = icmp ult i32 %add53, %sub4 216 br i1 %cmp5, label %for.body, label %for.cond54.preheader 217 218 for.body56: ; preds = %for.body56.preheader, %do.end66 219 %k.1200 = phi i32 [ %inc, %do.end66 ], [ %k.0.lcssa, %for.body56.preheader ] 220 %mul57 = mul i32 %k.1200, %0 221 %arrayidx58 = getelementptr inbounds float, float* %2, i32 %mul57 222 %start3 = call i32 @llvm.start.loop.iterations.i32(i32 %38) 223 br label %do.body59 224 225 do.body59: ; preds = %do.body59, %for.body56 226 %count.2 = phi i32 [ %0, %for.body56 ], [ %94, %do.body59 ] 227 %pInT.2 = phi float* [ %pIn, %for.body56 ], [ %add.ptr61, %do.body59 ] 228 %pCos0.1 = phi float* [ %arrayidx58, %for.body56 ], [ %add.ptr62, %do.body59 ] 229 %sumVec.1 = phi <4 x float> [ zeroinitializer, %for.body56 ], [ %93, %do.body59 ] 230 %89 = phi i32 [ %start3, %for.body56 ], [ %95, %do.body59 ] 231 %pInT.21 = bitcast float* %pInT.2 to <4 x float>* 232 %pCos0.12 = bitcast float* %pCos0.1 to <4 x float>* 233 %90 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %count.2) 234 %91 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pInT.21, i32 4, <4 x i1> %90, <4 x float> zeroinitializer) 235 %92 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pCos0.12, i32 4, <4 x i1> %90, <4 x float> zeroinitializer) 236 %93 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %91, <4 x float> %92, <4 x float> %sumVec.1, <4 x i1> %90) 237 %add.ptr61 = getelementptr inbounds float, float* %pInT.2, i32 4 238 %add.ptr62 = getelementptr inbounds float, float* %pCos0.1, i32 4 239 %94 = add i32 %count.2, -4 240 %95 = call i32 @llvm.loop.decrement.reg.i32(i32 %89, i32 1) 241 %96 = icmp ne i32 %95, 0 242 br i1 %96, label %do.body59, label %do.end66 243 244 do.end66: ; preds = %do.body59 245 %97 = extractelement <4 x float> %93, i32 0 246 %98 = extractelement <4 x float> %93, i32 1 247 %add67 = fadd fast float %97, %98 248 %99 = extractelement <4 x float> %93, i32 2 249 %add68 = fadd fast float %add67, %99 250 %100 = extractelement <4 x float> %93, i32 3 251 %add69 = fadd fast float %add68, %100 252 %arrayidx70 = getelementptr inbounds float, float* %pOut, i32 %k.1200 253 store float %add69, float* %arrayidx70, align 4 254 %inc = add nuw i32 %k.1200, 1 255 %exitcond.not = icmp eq i32 %inc, %1 256 br i1 %exitcond.not, label %for.end72, label %for.body56 257 258 for.end72: ; preds = %do.end66, %for.cond54.preheader 259 ret void 260 } 261 262 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 263 declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2 264 declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 265 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #3 266 declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 267 declare i32 @llvm.start.loop.iterations.i32(i32) #4 268 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4 269 270... 271--- 272name: test 273alignment: 4 274exposesReturnsTwice: false 275legalized: false 276regBankSelected: false 277selected: false 278failedISel: false 279tracksRegLiveness: true 280hasWinCFI: false 281registers: [] 282liveins: 283 - { reg: '$r0', virtual-reg: '' } 284 - { reg: '$r1', virtual-reg: '' } 285 - { reg: '$r2', virtual-reg: '' } 286frameInfo: 287 isFrameAddressTaken: false 288 isReturnAddressTaken: false 289 hasStackMap: false 290 hasPatchPoint: false 291 stackSize: 112 292 offsetAdjustment: 0 293 maxAlignment: 8 294 adjustsStack: false 295 hasCalls: false 296 stackProtector: '' 297 maxCallFrameSize: 0 298 cvBytesOfCalleeSavedRegisters: 0 299 hasOpaqueSPAdjustment: false 300 hasVAStart: false 301 hasMustTailInVarArgFunc: false 302 localFrameSize: 0 303 savePoint: '' 304 restorePoint: '' 305fixedStack: [] 306stack: 307 - { id: 0, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4, 308 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 309 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 310 - { id: 1, name: '', type: spill-slot, offset: -80, size: 4, alignment: 4, 311 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 312 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 313 - { id: 2, name: '', type: spill-slot, offset: -84, size: 4, alignment: 4, 314 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 315 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 316 - { id: 3, name: '', type: spill-slot, offset: -88, size: 4, alignment: 4, 317 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 318 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 319 - { id: 4, name: '', type: spill-slot, offset: -92, size: 4, alignment: 4, 320 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 321 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 322 - { id: 5, name: '', type: spill-slot, offset: -96, size: 4, alignment: 4, 323 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 324 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 325 - { id: 6, name: '', type: spill-slot, offset: -100, size: 4, alignment: 4, 326 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 327 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 328 - { id: 7, name: '', type: spill-slot, offset: -104, size: 4, alignment: 4, 329 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 330 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 331 - { id: 8, name: '', type: spill-slot, offset: -108, size: 4, alignment: 4, 332 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 333 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 334 - { id: 9, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 335 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 336 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 337 - { id: 10, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 338 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 339 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 340 - { id: 11, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 341 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 342 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 343 - { id: 12, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 344 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 345 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 346 - { id: 13, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 347 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 348 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 349 - { id: 14, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 350 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 351 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 352 - { id: 15, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 353 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 354 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 355 - { id: 16, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 356 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 357 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 358 - { id: 17, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 359 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 360 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 361 - { id: 18, name: '', type: spill-slot, offset: -48, size: 8, alignment: 8, 362 stack-id: default, callee-saved-register: '$d11', callee-saved-restored: true, 363 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 364 - { id: 19, name: '', type: spill-slot, offset: -56, size: 8, alignment: 8, 365 stack-id: default, callee-saved-register: '$d10', callee-saved-restored: true, 366 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 367 - { id: 20, name: '', type: spill-slot, offset: -64, size: 8, alignment: 8, 368 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true, 369 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 370 - { id: 21, name: '', type: spill-slot, offset: -72, size: 8, alignment: 8, 371 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true, 372 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 373callSites: [] 374constants: [] 375machineFunctionInfo: {} 376body: | 377 bb.0.entry: 378 successors: %bb.1(0x80000000) 379 liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr, $d8, $d9, $d10, $d11 380 381 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 382 frame-setup CFI_INSTRUCTION def_cfa_offset 36 383 frame-setup CFI_INSTRUCTION offset $lr, -4 384 frame-setup CFI_INSTRUCTION offset $r11, -8 385 frame-setup CFI_INSTRUCTION offset $r10, -12 386 frame-setup CFI_INSTRUCTION offset $r9, -16 387 frame-setup CFI_INSTRUCTION offset $r8, -20 388 frame-setup CFI_INSTRUCTION offset $r7, -24 389 frame-setup CFI_INSTRUCTION offset $r6, -28 390 frame-setup CFI_INSTRUCTION offset $r5, -32 391 frame-setup CFI_INSTRUCTION offset $r4, -36 392 $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 393 frame-setup CFI_INSTRUCTION def_cfa_offset 40 394 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9, killed $d10, killed $d11 395 frame-setup CFI_INSTRUCTION def_cfa_offset 72 396 frame-setup CFI_INSTRUCTION offset $d11, -48 397 frame-setup CFI_INSTRUCTION offset $d10, -56 398 frame-setup CFI_INSTRUCTION offset $d9, -64 399 frame-setup CFI_INSTRUCTION offset $d8, -72 400 $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 401 frame-setup CFI_INSTRUCTION def_cfa_offset 112 402 renamable $r4 = tLDRi renamable $r0, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.NumInputs) 403 $r5 = tMOVr killed $r1, 14 /* CC::al */, $noreg 404 renamable $r11 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.pDCTCoefs34) 405 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 406 $r1 = tMOVr $r4, 14 /* CC::al */, $noreg 407 tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 408 t2IT 10, 8, implicit-def $itstate 409 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate 410 renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg 411 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg 412 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 413 renamable $r3 = tLDRi killed renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.NumFilters) 414 $r0 = tMOVr $r4, 14 /* CC::al */, $noreg 415 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 416 $r1 = tMOVr $r5, 14 /* CC::al */, $noreg 417 $lr = t2DoLoopStart renamable $lr 418 419 bb.1.do.body (align 4): 420 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 421 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r11 422 423 renamable $vpr = MVE_VCTP32 renamable $r0, 0, $noreg 424 MVE_VPST 4, implicit $vpr 425 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.pInT.033, align 4) 426 renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q0 427 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 428 renamable $lr = t2LoopDec killed renamable $lr, 1 429 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 430 tB %bb.2, 14 /* CC::al */, $noreg 431 432 bb.2.do.end: 433 successors: %bb.3(0x40000000), %bb.7(0x40000000) 434 liveins: $q0, $r2, $r3, $r4, $r5, $r11 435 436 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg 437 renamable $r0, dead $cpsr = tSUBi3 renamable $r3, 4, 14 /* CC::al */, $noreg 438 tSTRspi killed renamable $r3, $sp, 1, 14 /* CC::al */, $noreg :: (store 4 into %stack.8) 439 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg 440 tSTRspi renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) 441 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 442 renamable $s2 = VLDRS renamable $r11, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.2) 443 tCMPi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr 444 renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 445 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 446 VSTRS killed renamable $s0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.pOut) 447 t2Bcc %bb.7, 3 /* CC::lo */, killed $cpsr 448 449 bb.3.for.body.lr.ph: 450 successors: %bb.4(0x80000000) 451 liveins: $r0, $r2, $r4, $r5, $r11 452 453 renamable $r6 = t2ADDri renamable $r5, 16, 14 /* CC::al */, $noreg, $noreg 454 renamable $r1, dead $cpsr = tSUBi3 renamable $r4, 4, 14 /* CC::al */, $noreg 455 tSTRspi killed renamable $r6, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %stack.5) 456 renamable $r6, dead $cpsr = tLSLri renamable $r4, 4, 14 /* CC::al */, $noreg 457 tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 458 tSTRspi killed renamable $r6, $sp, 3, 14 /* CC::al */, $noreg :: (store 4 into %stack.6) 459 t2IT 10, 8, implicit-def $itstate 460 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate 461 renamable $r7 = t2ADDrs renamable $r4, renamable $r4, 10, 14 /* CC::al */, $noreg, $noreg 462 renamable $r1, dead $cpsr = tMVN killed renamable $r1, 14 /* CC::al */, $noreg 463 renamable $r1 = tADDhirr killed renamable $r1, renamable $r4, 14 /* CC::al */, $noreg 464 renamable $r12 = t2ADDrs renamable $r11, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 465 renamable $r3 = t2ADDrs renamable $r11, renamable $r4, 26, 14 /* CC::al */, $noreg, $noreg 466 renamable $lr = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg 467 renamable $r7 = t2ADDrs renamable $r11, renamable $r4, 34, 14 /* CC::al */, $noreg, $noreg 468 renamable $r1 = nuw nsw t2ADDrs renamable $r0, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 469 renamable $r6 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg 470 renamable $r12 = t2ADDri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg 471 tSTRspi killed renamable $r1, $sp, 2, 14 /* CC::al */, $noreg :: (store 4 into %stack.7) 472 renamable $r1 = t2ADDri killed renamable $lr, 16, 14 /* CC::al */, $noreg, $noreg 473 renamable $r10 = t2ADDri killed renamable $r7, 16, 14 /* CC::al */, $noreg, $noreg 474 tSTRspi renamable $r4, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) 475 t2STRDi8 $r11, $r5, $sp, 20, 14 /* CC::al */, $noreg :: (store 4 into %stack.4), (store 4 into %stack.3) 476 477 bb.4.for.body (align 4): 478 successors: %bb.5(0x80000000) 479 liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r10, $r11, $r12 480 481 renamable $r3 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg 482 renamable $r7, dead $cpsr = nuw nsw tADDi3 renamable $r0, 1, 14 /* CC::al */, $noreg 483 renamable $r8 = nuw nsw t2ADDri renamable $r0, 2, 14 /* CC::al */, $noreg, $noreg 484 tSTRspi renamable $r7, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) 485 renamable $r9 = t2ADDri renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg 486 renamable $r7, dead $cpsr = tMUL renamable $r4, killed renamable $r7, 14 /* CC::al */, $noreg 487 renamable $q0 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg :: (load 16 from %ir.39, align 4) 488 renamable $r3 = t2ADDrs renamable $r11, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg 489 renamable $r5 = t2MUL renamable $r8, renamable $r4, 14 /* CC::al */, $noreg 490 renamable $r4 = t2MUL renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg 491 renamable $r7 = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg 492 renamable $r5 = t2ADDrs renamable $r11, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg 493 renamable $r4 = t2ADDrs killed renamable $r11, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 494 renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %ir.41, align 4) 495 renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q3 496 renamable $q1 = MVE_VLDRWU32 killed renamable $r7, 0, 0, $noreg :: (load 16 from %ir.44, align 4) 497 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 498 renamable $q1 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg :: (load 16 from %ir.47, align 4) 499 renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 500 renamable $q4 = MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.50, align 4) 501 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q4, killed renamable $q0, 0, $noreg, undef renamable $q0 502 renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.7) 503 $r3 = tMOVr $r10, 14 /* CC::al */, $noreg 504 $r5 = tMOVr $r1, 14 /* CC::al */, $noreg 505 $r4 = tMOVr $r12, 14 /* CC::al */, $noreg 506 $lr = t2DoLoopStart renamable $lr 507 $r7 = tMOVr $r6, 14 /* CC::al */, $noreg 508 renamable $r11 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %stack.5) 509 510 bb.5.do.body24 (align 4): 511 successors: %bb.5(0x7c000000), %bb.6(0x04000000) 512 liveins: $lr, $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 513 514 renamable $r11, renamable $q4 = MVE_VLDRWU32_post killed renamable $r11, 16, 0, $noreg :: (load 16 from %ir.lsr.iv4, align 4) 515 renamable $r7, renamable $q5 = MVE_VLDRWU32_post killed renamable $r7, 16, 0, $noreg :: (load 16 from %ir.lsr.iv911, align 4) 516 renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q3, renamable $q4, killed renamable $q5, 0, $noreg 517 renamable $r4, renamable $q5 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1618, align 4) 518 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q2, renamable $q4, killed renamable $q5, 0, $noreg 519 renamable $r5, renamable $q5 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load 16 from %ir.lsr.iv2325, align 4) 520 renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q1, renamable $q4, killed renamable $q5, 0, $noreg 521 renamable $r3, renamable $q5 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg :: (load 16 from %ir.lsr.iv3032, align 4) 522 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q4, killed renamable $q5, 0, $noreg 523 renamable $lr = t2LoopDec killed renamable $lr, 1 524 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr 525 tB %bb.6, 14 /* CC::al */, $noreg 526 527 bb.6.do.end33: 528 successors: %bb.4(0x7c000000), %bb.7(0x04000000) 529 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12 530 531 renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg 532 renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg 533 renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg 534 renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg 535 renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3 536 renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2 537 renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg 538 renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg 539 renamable $r7 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) 540 renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg 541 renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg 542 renamable $r3 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg 543 renamable $r7 = t2ADDrs renamable $r2, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg 544 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1 545 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 546 VSTRS killed renamable $s12, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.arrayidx37) 547 VSTRS killed renamable $s8, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.arrayidx42) 548 renamable $r3 = t2ADDrs renamable $r2, killed renamable $r8, 18, 14 /* CC::al */, $noreg, $noreg 549 renamable $r7 = t2ADDrs renamable $r2, killed renamable $r9, 18, 14 /* CC::al */, $noreg, $noreg 550 VSTRS killed renamable $s4, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.arrayidx47) 551 VSTRS killed renamable $s0, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.arrayidx52) 552 $r11, $r5 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load 4 from %stack.4), (load 4 from %stack.3) 553 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 554 renamable $r7 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load 4 from %stack.6) 555 renamable $r3 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) 556 renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) 557 renamable $r6 = tADDhirr killed renamable $r6, renamable $r7, 14 /* CC::al */, $noreg 558 renamable $r12 = tADDhirr killed renamable $r12, renamable $r7, 14 /* CC::al */, $noreg 559 renamable $r1 = tADDhirr killed renamable $r1, renamable $r7, 14 /* CC::al */, $noreg 560 tCMPr renamable $r0, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $cpsr 561 renamable $r10 = tADDhirr killed renamable $r10, killed renamable $r7, 14 /* CC::al */, $noreg 562 t2Bcc %bb.4, 3 /* CC::lo */, killed $cpsr 563 564 bb.7.for.cond54.preheader: 565 successors: %bb.8(0x40000000), %bb.12(0x40000000) 566 liveins: $r0, $r2, $r4, $r5, $r11 567 568 renamable $r12 = t2LDRi12 $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.8) 569 tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr 570 tBcc %bb.12, 2 /* CC::hs */, killed $cpsr 571 572 bb.8.for.body56.preheader: 573 successors: %bb.9(0x80000000) 574 liveins: $r0, $r2, $r4, $r5, $r11, $r12 575 576 $r1 = tMOVr $r4, 14 /* CC::al */, $noreg 577 tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 578 t2IT 10, 8, implicit-def $itstate 579 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate 580 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 581 renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg 582 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg 583 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 584 585 bb.9.for.body56 (align 4): 586 successors: %bb.13(0x80000000) 587 liveins: $r0, $r2, $r3, $r4, $r5, $r11, $r12 588 589 renamable $r1 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg 590 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 591 renamable $r1 = t2ADDrs renamable $r11, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg 592 $r6 = tMOVr $r4, 14 /* CC::al */, $noreg 593 $r7 = tMOVr $r5, 14 /* CC::al */, $noreg 594 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 595 $lr = t2DoLoopStart renamable $r3 596 597 bb.13: 598 successors: %bb.10(0x80000000) 599 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 600 601 bb.10.do.body59 (align 4): 602 successors: %bb.10(0x7c000000), %bb.11(0x04000000) 603 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 604 605 renamable $vpr = MVE_VCTP32 renamable $r6, 0, $noreg 606 MVE_VPST 2, implicit $vpr 607 renamable $r7, renamable $q1 = MVE_VLDRWU32_post killed renamable $r7, 16, 1, renamable $vpr :: (load 16 from %ir.pInT.21, align 4) 608 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.pCos0.12, align 4) 609 renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr 610 renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg 611 renamable $lr = t2LoopDec killed renamable $lr, 1 612 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr 613 tB %bb.11, 14 /* CC::al */, $noreg 614 615 bb.11.do.end66: 616 successors: %bb.12(0x04000000), %bb.9(0x7c000000) 617 liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12 618 619 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg 620 renamable $r1 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg 621 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg 622 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg 623 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 624 tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr 625 VSTRS killed renamable $s0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.arrayidx70) 626 tBcc %bb.9, 1 /* CC::ne */, killed $cpsr 627 628 bb.12.for.end72: 629 $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg 630 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11 631 $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg 632 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc 633 634... 635