1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6  target triple = "thumbv8.1m.main"
7
8  define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
9  entry:
10    %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
11    %scevgep = getelementptr i32, i32* %a, i32 -1
12    %scevgep4 = getelementptr i32, i32* %c, i32 -1
13    %scevgep8 = getelementptr i32, i32* %b, i32 -1
14    br label %for.header
15
16  for.body:                                         ; preds = %for.header
17    %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
18    %ld1 = load i32, i32* %scevgep11, align 4
19    %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1
20    %ld2 = load i32, i32* %scevgep7, align 4
21    %mul = mul nsw i32 %ld2, %ld1
22    %scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1
23    store i32 %mul, i32* %scevgep3, align 4
24    %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
25    %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
26    %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
27    %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
28    %cmp = icmp ne i32 %count.next, 0
29    br i1 %cmp, label %for.header, label %for.cond.cleanup
30
31  for.cond.cleanup:                                 ; preds = %for.body
32    ret void
33
34  for.header:                                       ; preds = %for.body, %entry
35    %lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ]
36    %lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ]
37    %lsr.iv1 = phi i32* [ %scevgep, %entry ], [ %scevgep2, %for.body ]
38    %count = phi i32 [ %start, %entry ], [ %count.next, %for.body ]
39    br label %for.body
40  }
41
42  ; Function Attrs: nounwind
43  declare i32 @llvm.arm.space(i32 immarg, i32) #0
44
45  ; Function Attrs: noduplicate nounwind
46  declare i32 @llvm.start.loop.iterations.i32(i32) #1
47
48  ; Function Attrs: noduplicate nounwind
49  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
50
51  attributes #0 = { nounwind }
52  attributes #1 = { noduplicate nounwind }
53
54...
55---
56name:            size_limit
57alignment:       2
58exposesReturnsTwice: false
59legalized:       false
60regBankSelected: false
61selected:        false
62failedISel:      false
63tracksRegLiveness: true
64hasWinCFI:       false
65registers:       []
66liveins:
67  - { reg: '$r0', virtual-reg: '' }
68  - { reg: '$r1', virtual-reg: '' }
69  - { reg: '$r2', virtual-reg: '' }
70  - { reg: '$r3', virtual-reg: '' }
71frameInfo:
72  isFrameAddressTaken: false
73  isReturnAddressTaken: false
74  hasStackMap:     false
75  hasPatchPoint:   false
76  stackSize:       40
77  offsetAdjustment: 0
78  maxAlignment:    4
79  adjustsStack:    false
80  hasCalls:        false
81  stackProtector:  ''
82  maxCallFrameSize: 0
83  cvBytesOfCalleeSavedRegisters: 0
84  hasOpaqueSPAdjustment: false
85  hasVAStart:      false
86  hasMustTailInVarArgFunc: false
87  localFrameSize:  0
88  savePoint:       ''
89  restorePoint:    ''
90fixedStack:      []
91stack:
92  - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
93      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
94      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
95  - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
96      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
97      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
98  - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
99      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
100      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
101  - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
102      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
103      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
104  - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
105      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
106      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
107  - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
108      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
109      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
110  - { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
111      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
112      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
113  - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
114      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
115      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
116  - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
117      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
118      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
119  - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
120      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
121      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
122callSites:       []
123constants:       []
124machineFunctionInfo: {}
125body:             |
126  ; CHECK-LABEL: name: size_limit
127  ; CHECK: bb.0.entry:
128  ; CHECK:   successors: %bb.3(0x80000000)
129  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
130  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
131  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
132  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
133  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
134  ; CHECK:   $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg
135  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 40
136  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
137  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
138  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
139  ; CHECK:   tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
140  ; CHECK:   tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
141  ; CHECK:   tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
142  ; CHECK:   tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
143  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
144  ; CHECK: bb.1.for.body:
145  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
146  ; CHECK:   $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load 4 from %stack.4)
147  ; CHECK:   renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11)
148  ; CHECK:   $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %stack.5)
149  ; CHECK:   renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
150  ; CHECK:   renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg
151  ; CHECK:   $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load 4 from %stack.6)
152  ; CHECK:   early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3)
153  ; CHECK:   $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.7)
154  ; CHECK:   $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg
155  ; CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
156  ; CHECK:   $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
157  ; CHECK:   tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
158  ; CHECK:   tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
159  ; CHECK:   tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
160  ; CHECK:   t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
161  ; CHECK:   tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
162  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
163  ; CHECK: bb.2.for.cond.cleanup:
164  ; CHECK:   $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg
165  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
166  ; CHECK: bb.3.for.header:
167  ; CHECK:   successors: %bb.1(0x80000000)
168  ; CHECK:   $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.3)
169  ; CHECK:   $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
170  ; CHECK:   $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
171  ; CHECK:   $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
172  ; CHECK:   tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.7)
173  ; CHECK:   tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store 4 into %stack.6)
174  ; CHECK:   tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store 4 into %stack.5)
175  ; CHECK:   tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store 4 into %stack.4)
176  ; CHECK:   tB %bb.1, 14 /* CC::al */, $noreg
177  bb.0.entry:
178    successors: %bb.3(0x80000000)
179    liveins: $r0, $r1, $r2, $r3, $r7, $lr
180
181    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
182    frame-setup CFI_INSTRUCTION def_cfa_offset 8
183    frame-setup CFI_INSTRUCTION offset $lr, -4
184    frame-setup CFI_INSTRUCTION offset $r7, -8
185    $sp = frame-setup tSUBspi $sp, 8, 14, $noreg
186    frame-setup CFI_INSTRUCTION def_cfa_offset 40
187    $lr = t2DoLoopStart renamable $r3
188    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
189    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
190    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
191    tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
192    tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1)
193    tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
194    tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3)
195    tB %bb.3, 14, $noreg
196
197  bb.1.for.body:
198    successors: %bb.3(0x40000000), %bb.2(0x40000000)
199
200    $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4)
201    renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11)
202    $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5)
203    renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
204    renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg
205    $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6)
206    early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3)
207    $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7)
208    $lr = tMOVr killed $r1, 14, $noreg
209    renamable $lr = t2LoopDec killed renamable $lr, 1
210    $r12 = tMOVr $lr, 14, $noreg
211    tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
212    tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1)
213    tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
214    t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3)
215    t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr
216    tB %bb.2, 14, $noreg
217
218  bb.2.for.cond.cleanup:
219    $sp = tADDspi $sp, 8, 14, $noreg
220    tPOP_RET 14, $noreg, def $r7, def $pc
221
222  bb.3.for.header:
223    successors: %bb.1(0x80000000)
224
225    $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3)
226    $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2)
227    $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1)
228    $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
229    tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7)
230    tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6)
231    tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5)
232    tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4)
233    tB %bb.1, 14, $noreg
234
235...
236