1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3--- |
4  define dso_local void @incorrect_sub_8(i8* noalias nocapture %A, i8* noalias nocapture readonly %B, i8* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
5  entry:
6    %cmp8 = icmp sgt i32 %N, 0
7    %0 = add i32 %N, 3
8    %1 = lshr i32 %0, 2
9    %2 = shl nuw i32 %1, 2
10    %3 = add i32 %2, -4
11    %4 = lshr i32 %3, 2
12    %5 = add nuw nsw i32 %4, 1
13    br i1 %cmp8, label %vector.ph, label %for.cond.cleanup
14
15  vector.ph:                                        ; preds = %entry
16    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
17    br label %vector.body
18
19  vector.body:                                      ; preds = %vector.body, %vector.ph
20    %lsr.iv17 = phi i8* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
21    %lsr.iv14 = phi i8* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
22    %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
23    %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]
24    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
25    %lsr.iv13 = bitcast i8* %lsr.iv to <16 x i8>*
26    %lsr.iv1416 = bitcast i8* %lsr.iv14 to <16 x i8>*
27    %lsr.iv1719 = bitcast i8* %lsr.iv17 to <16 x i8>*
28    %8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)
29    %9 = sub i32 %7, 15
30    %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv13, i32 4, <16 x i1> %8, <16 x i8> undef)
31    %wide.masked.load12 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv1416, i32 4, <16 x i1> %8, <16 x i8> undef)
32    %10 = add nsw <16 x i8> %wide.masked.load12, %wide.masked.load
33    call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %10, <16 x i8>* %lsr.iv1719, i32 4, <16 x i1> %8)
34    %scevgep = getelementptr i8, i8* %lsr.iv, i32 16
35    %scevgep15 = getelementptr i8, i8* %lsr.iv14, i32 16
36    %scevgep18 = getelementptr i8, i8* %lsr.iv17, i32 16
37    %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
38    %12 = icmp ne i32 %11, 0
39    br i1 %12, label %vector.body, label %for.cond.cleanup
40
41  for.cond.cleanup:                                 ; preds = %vector.body, %entry
42    ret void
43  }
44  declare i32 @llvm.start.loop.iterations.i32(i32)
45  declare <16 x i1> @llvm.arm.mve.vctp8(i32)
46  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
47  declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
48  declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
49  declare void @llvm.stackprotector(i8*, i8**)
50...
51---
52name:            incorrect_sub_8
53alignment:       2
54exposesReturnsTwice: false
55legalized:       false
56regBankSelected: false
57selected:        false
58failedISel:      false
59tracksRegLiveness: true
60hasWinCFI:       false
61registers:       []
62liveins:
63  - { reg: '$r0', virtual-reg: '' }
64  - { reg: '$r1', virtual-reg: '' }
65  - { reg: '$r2', virtual-reg: '' }
66  - { reg: '$r3', virtual-reg: '' }
67frameInfo:
68  isFrameAddressTaken: false
69  isReturnAddressTaken: false
70  hasStackMap:     false
71  hasPatchPoint:   false
72  stackSize:       8
73  offsetAdjustment: 0
74  maxAlignment:    4
75  adjustsStack:    false
76  hasCalls:        false
77  stackProtector:  ''
78  maxCallFrameSize: 0
79  cvBytesOfCalleeSavedRegisters: 0
80  hasOpaqueSPAdjustment: false
81  hasVAStart:      false
82  hasMustTailInVarArgFunc: false
83  localFrameSize:  0
84  savePoint:       ''
85  restorePoint:    ''
86fixedStack:      []
87stack:
88  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
89      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
90      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
91  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
92      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
93      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
94callSites:       []
95constants:       []
96machineFunctionInfo: {}
97body:             |
98  ; CHECK-LABEL: name: incorrect_sub_8
99  ; CHECK: bb.0.entry:
100  ; CHECK:   successors: %bb.1(0x80000000)
101  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
102  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
103  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
104  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
105  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
106  ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
107  ; CHECK:   t2IT 11, 8, implicit-def $itstate
108  ; CHECK:   tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
109  ; CHECK: bb.1.vector.ph:
110  ; CHECK:   successors: %bb.2(0x80000000)
111  ; CHECK:   liveins: $r0, $r1, $r2, $r3
112  ; CHECK:   renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
113  ; CHECK:   renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
114  ; CHECK:   renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
115  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
116  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
117  ; CHECK:   $lr = t2DLS killed renamable $lr
118  ; CHECK: bb.2.vector.body:
119  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
120  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
121  ; CHECK:   renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
122  ; CHECK:   MVE_VPST 4, implicit $vpr
123  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
124  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
125  ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg
126  ; CHECK:   renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
127  ; CHECK:   MVE_VPST 8, implicit $vpr
128  ; CHECK:   renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
129  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
130  ; CHECK: bb.3.for.cond.cleanup:
131  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
132  bb.0.entry:
133    successors: %bb.1(0x80000000)
134    liveins: $r0, $r1, $r2, $r3, $r7, $lr
135
136    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
137    frame-setup CFI_INSTRUCTION def_cfa_offset 8
138    frame-setup CFI_INSTRUCTION offset $lr, -4
139    frame-setup CFI_INSTRUCTION offset $r7, -8
140    tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
141    t2IT 11, 8, implicit-def $itstate
142    tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
143
144  bb.1.vector.ph:
145    successors: %bb.2(0x80000000)
146    liveins: $r0, $r1, $r2, $r3, $r7, $lr
147
148    renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
149    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
150    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
151    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
152    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
153    $lr = t2DoLoopStart renamable $lr
154
155  bb.2.vector.body:
156    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
157    liveins: $lr, $r0, $r1, $r2, $r3
158
159    renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
160    MVE_VPST 4, implicit $vpr
161    renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
162    renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
163    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg
164    renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
165    MVE_VPST 8, implicit $vpr
166    renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
167    renamable $lr = t2LoopDec killed renamable $lr, 1
168    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
169    tB %bb.3, 14, $noreg
170
171  bb.3.for.cond.cleanup:
172    tPOP_RET 14, $noreg, def $r7, def $pc
173
174...
175