1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# Test that, even if vpsels are allowed, that they aren't inserted into a vpt 5# block - which would cause an assert here because of the number of insts in 6# the block. 7 8--- | 9 define dso_local i32 @vpsel_after_vpt(i16* nocapture readonly %a, i16* nocapture readonly %b, i16* nocapture readonly %c, i16* nocapture readonly %d, i32 %N) local_unnamed_addr #0 { 10 entry: 11 %cmp9 = icmp eq i32 %N, 0 12 %tmp = add i32 %N, 3 13 %tmp1 = lshr i32 %tmp, 2 14 %tmp2 = shl nuw i32 %tmp1, 2 15 %tmp3 = add i32 %tmp2, -4 16 %tmp4 = lshr i32 %tmp3, 2 17 %tmp5 = add nuw nsw i32 %tmp4, 1 18 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 19 20 vector.ph: ; preds = %entry 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 22 br label %vector.body 23 24 vector.body: ; preds = %vector.body, %vector.ph 25 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 26 %lsr.iv.d = phi i16* [ %scevgep.d, %vector.body ], [ %d, %vector.ph ] 27 %lsr.iv.c = phi i16* [ %scevgep.c, %vector.body ], [ %c, %vector.ph ] 28 %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ] 29 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 30 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp14, %vector.body ] 31 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 32 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 33 %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>* 34 %lsr.iv1820.c = bitcast i16* %lsr.iv.c to <4 x i16>* 35 %lsr.iv17.d = bitcast i16* %lsr.iv.d to <4 x i16>* 36 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 37 %tmp9 = sub i32 %tmp7, 4 38 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 39 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 40 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 41 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32> 42 %wide.masked.load.c = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820.c, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 43 %sext.load.c = sext <4 x i16> %wide.masked.load.c to <4 x i32> 44 %wide.masked.load.d = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17.d, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 45 %sext.load.d = sext <4 x i16> %wide.masked.load.d to <4 x i32> 46 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10 47 %mul.2 = mul nsw <4 x i32> %sext.load.c, %sext.load.d 48 %tmp13 = add <4 x i32> %tmp12, %mul.2 49 %acc = add <4 x i32> %tmp13, %vec.phi 50 %tmp14 = select <4 x i1> %tmp8, <4 x i32> %acc, <4 x i32> %vec.phi 51 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 52 %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4 53 %scevgep.c = getelementptr i16, i16* %lsr.iv.c, i32 4 54 %scevgep.d = getelementptr i16, i16* %lsr.iv.d, i32 4 55 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 56 %tmp16 = icmp ne i32 %tmp15, 0 57 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 58 br i1 %tmp16, label %vector.body, label %middle.block 59 60 middle.block: ; preds = %vector.body 61 %tmp17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp14) 62 br label %for.cond.cleanup 63 64 for.cond.cleanup: ; preds = %middle.block, %entry 65 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp17, %middle.block ] 66 ret i32 %res.0.lcssa 67 } 68 declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1 69 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2 70 declare i32 @llvm.start.loop.iterations.i32(i32) #3 71 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 72 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 73 74... 75--- 76name: vpsel_after_vpt 77alignment: 2 78exposesReturnsTwice: false 79legalized: false 80regBankSelected: false 81selected: false 82failedISel: false 83tracksRegLiveness: true 84hasWinCFI: false 85registers: [] 86liveins: 87 - { reg: '$r0', virtual-reg: '' } 88 - { reg: '$r1', virtual-reg: '' } 89 - { reg: '$r2', virtual-reg: '' } 90 - { reg: '$r3', virtual-reg: '' } 91frameInfo: 92 isFrameAddressTaken: false 93 isReturnAddressTaken: false 94 hasStackMap: false 95 hasPatchPoint: false 96 stackSize: 16 97 offsetAdjustment: 0 98 maxAlignment: 4 99 adjustsStack: false 100 hasCalls: false 101 stackProtector: '' 102 maxCallFrameSize: 0 103 cvBytesOfCalleeSavedRegisters: 0 104 hasOpaqueSPAdjustment: false 105 hasVAStart: false 106 hasMustTailInVarArgFunc: false 107 localFrameSize: 0 108 savePoint: '' 109 restorePoint: '' 110fixedStack: 111 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 112 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 113 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 114stack: 115 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 116 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 117 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 118 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 119 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 120 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 121 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 122 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 123 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 124 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 125 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 126 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 127callSites: [] 128constants: [] 129machineFunctionInfo: {} 130body: | 131 ; CHECK-LABEL: name: vpsel_after_vpt 132 ; CHECK: bb.0.entry: 133 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 134 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 135 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 136 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 137 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 138 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 139 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 140 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 141 ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) 142 ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 143 ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr 144 ; CHECK: bb.1.vector.ph: 145 ; CHECK: successors: %bb.2(0x80000000) 146 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 147 ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 148 ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 149 ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg 150 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 151 ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg 152 ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg 153 ; CHECK: dead $lr = t2DLS renamable $r5 154 ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg 155 ; CHECK: bb.2.vector.body: 156 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 157 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 158 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg 159 ; CHECK: MVE_VPST 2, implicit $vpr 160 ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) 161 ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) 162 ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) 163 ; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 164 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 165 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 166 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 167 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 168 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 169 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 170 ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 171 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr 172 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 173 ; CHECK: bb.3.middle.block: 174 ; CHECK: liveins: $q0 175 ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 176 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 177 ; CHECK: bb.4: 178 ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 179 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 180 bb.0.entry: 181 successors: %bb.4(0x30000000), %bb.1(0x50000000) 182 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr 183 184 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp 185 frame-setup CFI_INSTRUCTION def_cfa_offset 16 186 frame-setup CFI_INSTRUCTION offset $lr, -4 187 frame-setup CFI_INSTRUCTION offset $r7, -8 188 frame-setup CFI_INSTRUCTION offset $r5, -12 189 frame-setup CFI_INSTRUCTION offset $r4, -16 190 renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) 191 t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr 192 tBcc %bb.4, 0, killed $cpsr 193 194 bb.1.vector.ph: 195 successors: %bb.2(0x80000000) 196 liveins: $r0, $r1, $r2, $r3, $r12 197 198 renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg 199 renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg 200 renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg 201 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 202 renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg 203 renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg 204 $lr = t2DoLoopStart renamable $r5 205 $r4 = tMOVr killed $r5, 14, $noreg 206 207 bb.2.vector.body: 208 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 209 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 210 211 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg 212 MVE_VPST 2, implicit $vpr 213 renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17.d, align 2) 214 renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820.c, align 2) 215 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) 216 renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 217 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 218 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 219 $lr = tMOVr $r4, 14, $noreg 220 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 221 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg 222 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 223 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 224 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr 225 renamable $lr = t2LoopDec killed renamable $lr, 1 226 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 227 tB %bb.3, 14, $noreg 228 229 bb.3.middle.block: 230 liveins: $q0 231 232 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 233 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 234 235 bb.4: 236 renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg 237 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 238 239... 240