1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
3
4# IT-block with 3 statements, all chained together.
5
6--- |
7  define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
8  entry:
9    %mul = shl i32 %blockSize, 1
10    %0 = add i32 %mul, 3
11    %1 = icmp slt i32 %mul, 4
12    %smin = select i1 %1, i32 %mul, i32 4
13    %2 = sub i32 %0, %smin
14    %3 = lshr i32 %2, 2
15    %4 = add nuw nsw i32 %3, 1
16    %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)
17    br label %do.body
18
19  do.body:                                          ; preds = %do.body, %entry
20    %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
21    %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
22    %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
23    %5 = phi i32 [ %start, %entry ], [ %9, %do.body ]
24    %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
25    %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
26    %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
27    %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
28    %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
29    tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
30    %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
31    %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
32    %sub = add nsw i32 %blkCnt.0, -4
33    %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
34    %10 = icmp ne i32 %9, 0
35    br i1 %10, label %do.body, label %do.end
36
37  do.end:                                           ; preds = %do.body
38    ret void
39  }
40  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
41  declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
42  declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
43  declare i32 @llvm.start.loop.iterations.i32(i32)
44  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
45
46...
47---
48name:            it_block_2_stmts
49alignment:       16
50exposesReturnsTwice: false
51legalized:       false
52regBankSelected: false
53selected:        false
54failedISel:      false
55tracksRegLiveness: true
56hasWinCFI:       false
57registers:       []
58liveins:
59  - { reg: '$r0', virtual-reg: '' }
60  - { reg: '$r1', virtual-reg: '' }
61  - { reg: '$r2', virtual-reg: '' }
62frameInfo:
63  isFrameAddressTaken: false
64  isReturnAddressTaken: false
65  hasStackMap:     false
66  hasPatchPoint:   false
67  stackSize:       8
68  offsetAdjustment: 0
69  maxAlignment:    4
70  adjustsStack:    false
71  hasCalls:        false
72  stackProtector:  ''
73  maxCallFrameSize: 0
74  cvBytesOfCalleeSavedRegisters: 0
75  hasOpaqueSPAdjustment: false
76  hasVAStart:      false
77  hasMustTailInVarArgFunc: false
78  localFrameSize:  0
79  savePoint:       ''
80  restorePoint:    ''
81fixedStack:      []
82stack:
83  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
84      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
85      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
86  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
87      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
88      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
89callSites:       []
90constants:
91  - id:              0
92    value:           '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
93    alignment:       16
94    isTargetSpecific: false
95machineFunctionInfo: {}
96body:             |
97  ; CHECK-LABEL: name: it_block_2_stmts
98  ; CHECK: bb.0.entry:
99  ; CHECK:   successors: %bb.1(0x80000000)
100  ; CHECK:   liveins: $lr, $r0, $r2, $r7
101  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
102  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
103  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
104  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
105  ; CHECK:   renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg
106  ; CHECK:   renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
107  ; CHECK:   tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
108  ; CHECK:   t2IT 11, 8, implicit-def $itstate
109  ; CHECK:   $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate
110  ; CHECK:   $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
111  ; CHECK:   $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
112  ; CHECK:   renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
113  ; CHECK:   dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
114  ; CHECK:   dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
115  ; CHECK:   renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
116  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
117  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
118  ; CHECK: bb.1.do.body (align 4):
119  ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
120  ; CHECK:   liveins: $lr, $q0, $r0, $r1
121  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
122  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
123  ; CHECK:   MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
124  ; CHECK:   renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
125  ; CHECK:   renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
126  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
127  ; CHECK: bb.2.do.end:
128  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
129  ; CHECK: bb.3 (align 16):
130  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
131  bb.0.entry:
132    successors: %bb.1(0x80000000)
133    liveins: $r0, $r1, $r2, $r7, $lr
134
135    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
136    frame-setup CFI_INSTRUCTION def_cfa_offset 8
137    frame-setup CFI_INSTRUCTION offset $lr, -4
138    frame-setup CFI_INSTRUCTION offset $r7, -8
139    renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
140    renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
141    tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
142    t2IT 11, 8, implicit-def $itstate
143    $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
144    $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
145    $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
146    renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
147    renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
148    renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
149    renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
150    renamable $r2 = tLEApcrel %const.0, 14, $noreg
151    renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
152    $lr = t2DoLoopStart renamable $lr
153
154  bb.1.do.body (align 4):
155    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
156    liveins: $lr, $q0, $r0, $r1, $r3
157
158    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
159    MVE_VPST 2, implicit $vpr
160    renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
161    renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
162    MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
163    renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
164    renamable $lr = t2LoopDec killed renamable $lr, 1
165    renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
166    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
167    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
168    tB %bb.2, 14, $noreg
169
170  bb.2.do.end:
171    tPOP_RET 14, $noreg, def $r7, def $pc
172
173  bb.3 (align 16):
174    CONSTPOOL_ENTRY 0, %const.0, 16
175
176...
177