1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
3
4# IT-block with 2 statements, which we don't support yet, so check that we do
5# not remove any of the iteration count statements.
6
7--- |
8  define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
9  entry:
10    %mul = shl i32 %blockSize, 1
11    %0 = add i32 %mul, 3
12    %1 = icmp slt i32 %mul, 4
13    %smin = select i1 %1, i32 %mul, i32 4
14    %2 = sub i32 %0, %smin
15    %3 = lshr i32 %2, 2
16    %4 = add nuw nsw i32 %3, 1
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)
18    br label %do.body
19
20  do.body:                                          ; preds = %do.body, %entry
21    %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
22    %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
23    %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
24    %5 = phi i32 [ %start, %entry ], [ %9, %do.body ]
25    %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
26    %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
27    %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
28    %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
29    %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
30    tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
31    %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
32    %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
33    %sub = add nsw i32 %blkCnt.0, -4
34    %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
35    %10 = icmp ne i32 %9, 0
36    br i1 %10, label %do.body, label %do.end
37
38  do.end:                                           ; preds = %do.body
39    ret void
40  }
41  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
42  declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
43  declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
44  declare i32 @llvm.start.loop.iterations.i32(i32)
45  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
46
47...
48---
49name:            it_block_2_stmts
50alignment:       16
51exposesReturnsTwice: false
52legalized:       false
53regBankSelected: false
54selected:        false
55failedISel:      false
56tracksRegLiveness: true
57hasWinCFI:       false
58registers:       []
59liveins:
60  - { reg: '$r0', virtual-reg: '' }
61  - { reg: '$r1', virtual-reg: '' }
62  - { reg: '$r2', virtual-reg: '' }
63frameInfo:
64  isFrameAddressTaken: false
65  isReturnAddressTaken: false
66  hasStackMap:     false
67  hasPatchPoint:   false
68  stackSize:       8
69  offsetAdjustment: 0
70  maxAlignment:    4
71  adjustsStack:    false
72  hasCalls:        false
73  stackProtector:  ''
74  maxCallFrameSize: 0
75  cvBytesOfCalleeSavedRegisters: 0
76  hasOpaqueSPAdjustment: false
77  hasVAStart:      false
78  hasMustTailInVarArgFunc: false
79  localFrameSize:  0
80  savePoint:       ''
81  restorePoint:    ''
82fixedStack:      []
83stack:
84  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
85      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
86      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
87  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
88      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
89      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
90callSites:       []
91constants:
92  - id:              0
93    value:           '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
94    alignment:       16
95    isTargetSpecific: false
96machineFunctionInfo: {}
97body:             |
98  ; CHECK-LABEL: name: it_block_2_stmts
99  ; CHECK: bb.0.entry:
100  ; CHECK:   successors: %bb.1(0x80000000)
101  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
102  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
103  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
104  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
105  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
106  ; CHECK:   renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
107  ; CHECK:   renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
108  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
109  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
110  ; CHECK: bb.1.do.body (align 4):
111  ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
112  ; CHECK:   liveins: $lr, $q0, $r0, $r1
113  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
114  ; CHECK:   renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
115  ; CHECK:   MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
116  ; CHECK:   renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
117  ; CHECK:   renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
118  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
119  ; CHECK: bb.2.do.end:
120  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
121  ; CHECK: bb.3 (align 16):
122  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
123  bb.0.entry:
124    successors: %bb.1(0x80000000)
125    liveins: $r0, $r1, $r2, $r7, $lr
126
127    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
128    frame-setup CFI_INSTRUCTION def_cfa_offset 8
129    frame-setup CFI_INSTRUCTION offset $lr, -4
130    frame-setup CFI_INSTRUCTION offset $r7, -8
131    renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
132    renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
133    tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
134    t2IT 11, 8, implicit-def $itstate
135    $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
136    $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
137    renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
138    renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
139    renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
140    renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
141    renamable $r2 = tLEApcrel %const.0, 14, $noreg
142    renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
143    $lr = t2DoLoopStart renamable $lr
144
145  bb.1.do.body (align 4):
146    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
147    liveins: $lr, $q0, $r0, $r1, $r3
148
149    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
150    MVE_VPST 2, implicit $vpr
151    renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
152    renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
153    MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
154    renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
155    renamable $lr = t2LoopDec killed renamable $lr, 1
156    renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
157    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
158    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
159    tB %bb.2, 14, $noreg
160
161  bb.2.do.end:
162    tPOP_RET 14, $noreg, def $r7, def $pc
163
164  bb.3 (align 16):
165    CONSTPOOL_ENTRY 0, %const.0, 16
166
167...
168