1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# TODO: We should be able to handle the VCMP -> VPST -> VCMP -> VCTP case. 5 6--- | 7 define dso_local arm_aapcs_vfpcc void @test(i32* noalias nocapture %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 { 8 entry: 9 %cmp9 = icmp eq i32 %N, 0 10 %tmp = add i32 %N, 3 11 %tmp1 = lshr i32 %tmp, 2 12 %tmp2 = shl nuw i32 %tmp1, 2 13 %tmp3 = add i32 %tmp2, -4 14 %tmp4 = lshr i32 %tmp3, 2 15 %tmp5 = add nuw nsw i32 %tmp4, 1 16 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 17 18 vector.ph: ; preds = %entry 19 %div = lshr i32 %N, 1 20 %trip.count.minus.1 = add i32 %N, -1 21 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 22 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 23 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 24 br label %vector.body 25 26 vector.body: ; preds = %vector.body, %vector.ph 27 %lsr.iv = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 28 %lsr.iv3 = phi i32* [ %scevgep4, %vector.body ], [ %b, %vector.ph ] 29 %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 30 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ] 31 %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ] 32 %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* 33 %lsr.iv35 = bitcast i32* %lsr.iv3 to <4 x i32>* 34 %tmp7 = insertelement <4 x i32> undef, i32 %div, i32 0 35 %tmp8 = shufflevector <4 x i32> %tmp7, <4 x i32> undef, <4 x i32> zeroinitializer 36 %tmp9 = icmp ult <4 x i32> %vec.ind, %tmp8 37 %lower = icmp uge <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1> 38 %tmp10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem) 39 %tmp11 = and <4 x i1> %tmp9, %tmp10 40 %pred = and <4 x i1> %tmp11, %lower 41 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv35, i32 4, <4 x i1> %pred, <4 x i32> undef) 42 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %wide.masked.load, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %pred) 43 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4> 44 %elts.rem.next = sub i32 %elts.rem, 4 45 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4 46 %scevgep4 = getelementptr i32, i32* %lsr.iv3, i32 4 47 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 48 %tmp13 = icmp ne i32 %tmp12, 0 49 %lsr.iv.next = add nsw i32 %lsr.iv, -1 50 br i1 %tmp13, label %vector.body, label %for.cond.cleanup 51 52 for.cond.cleanup: ; preds = %vector.body, %entry 53 ret void 54 } 55 56 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 57 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 58 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 59 declare i32 @llvm.start.loop.iterations.i32(i32) 60 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 61 62... 63--- 64name: test 65alignment: 16 66tracksRegLiveness: true 67registers: [] 68liveins: 69 - { reg: '$r0', virtual-reg: '' } 70 - { reg: '$r1', virtual-reg: '' } 71 - { reg: '$r2', virtual-reg: '' } 72frameInfo: 73 stackSize: 24 74 offsetAdjustment: 0 75 maxAlignment: 8 76fixedStack: [] 77stack: 78 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 79 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 80 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 81 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 82 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, 85 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87 - { id: 3, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8, 88 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true, 89 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 90callSites: [] 91constants: 92 - id: 0 93 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 94 alignment: 16 95 isTargetSpecific: false 96machineFunctionInfo: {} 97body: | 98 ; CHECK-LABEL: name: test 99 ; CHECK: bb.0.entry: 100 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 101 ; CHECK: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 102 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 103 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 104 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 105 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 106 ; CHECK: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 107 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 108 ; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16 109 ; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24 110 ; CHECK: tCBZ $r2, %bb.3 111 ; CHECK: bb.1.vector.ph: 112 ; CHECK: successors: %bb.2(0x80000000) 113 ; CHECK: liveins: $r0, $r1, $r2 114 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 115 ; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 116 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 117 ; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 118 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 119 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 120 ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 121 ; CHECK: dead $lr = t2DLS renamable $r3 122 ; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg 123 ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 124 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) 125 ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg 126 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 127 ; CHECK: bb.2.vector.body: 128 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 129 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 130 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 131 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 132 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 133 ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg 134 ; CHECK: MVE_VPST 1, implicit $vpr 135 ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr 136 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 137 ; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4) 138 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4) 139 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 140 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 141 ; CHECK: bb.3.for.cond.cleanup: 142 ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 143 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 144 ; CHECK: bb.4 (align 16): 145 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 146 bb.0.entry: 147 successors: %bb.3(0x30000000), %bb.1(0x50000000) 148 liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9 149 150 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 151 frame-setup CFI_INSTRUCTION def_cfa_offset 8 152 frame-setup CFI_INSTRUCTION offset $lr, -4 153 frame-setup CFI_INSTRUCTION offset $r4, -8 154 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 155 frame-setup CFI_INSTRUCTION def_cfa_offset 24 156 frame-setup CFI_INSTRUCTION offset $d9, -16 157 frame-setup CFI_INSTRUCTION offset $d8, -24 158 tCBZ $r2, %bb.3 159 160 bb.1.vector.ph: 161 successors: %bb.2(0x80000000) 162 liveins: $r0, $r1, $r2 163 164 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 165 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 166 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 167 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 168 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 169 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 170 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 171 $lr = t2DoLoopStart renamable $r3 172 $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg 173 renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 174 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) 175 renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg 176 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 177 178 bb.2.vector.body: 179 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 180 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 181 182 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 183 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 184 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 185 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg 186 MVE_VPST 1, implicit $vpr 187 renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr 188 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 189 renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4) 190 renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4) 191 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 192 renamable $lr = t2LoopDec killed renamable $lr, 1 193 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 194 tB %bb.3, 14 /* CC::al */, $noreg 195 196 bb.3.for.cond.cleanup: 197 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 198 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 199 200 bb.4 (align 16): 201 CONSTPOOL_ENTRY 0, %const.0, 16 202 203... 204