1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
3--- |
4
5  ; Function Attrs: nofree norecurse nounwind
6  define dso_local arm_aapcs_vfpcc void @test(i32* noalias nocapture %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
7  entry:
8    %cmp9 = icmp eq i32 %N, 0
9    %0 = add i32 %N, 3
10    %1 = lshr i32 %0, 2
11    %2 = shl nuw i32 %1, 2
12    %3 = add i32 %2, -4
13    %4 = lshr i32 %3, 2
14    %5 = add nuw nsw i32 %4, 1
15    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
16
17  vector.ph:                                        ; preds = %entry
18    %div = lshr i32 %N, 1
19    %trip.count.minus.1 = add i32 %N, -1
20    %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0
21    %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
22    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
23    br label %vector.body
24
25  vector.body:                                      ; preds = %vector.body, %vector.ph
26    %lsr.iv3 = phi i32* [ %scevgep4, %vector.body ], [ %b, %vector.ph ]
27    %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
28    %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]
29    %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]
30    %6 = phi i32 [ %start, %vector.ph ], [ %12, %vector.body ]
31    %lsr.iv35 = bitcast i32* %lsr.iv3 to <4 x i32>*
32    %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>*
33    %7 = insertelement <4 x i32> undef, i32 %div, i32 0
34    %8 = shufflevector <4 x i32> %7, <4 x i32> undef, <4 x i32> zeroinitializer
35    %9 = icmp ult <4 x i32> %vec.ind, %8
36    %10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)
37    %11 = and <4 x i1> %9, %10
38    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv35, i32 4, <4 x i1> %11, <4 x i32> undef)
39    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %wide.masked.load, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %11)
40    %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
41    %elts.rem.next = sub i32 %elts.rem, 4
42    %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4
43    %scevgep4 = getelementptr i32, i32* %lsr.iv3, i32 4
44    %12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
45    %13 = icmp ne i32 %12, 0
46    br i1 %13, label %vector.body, label %for.cond.cleanup
47
48  for.cond.cleanup:                                 ; preds = %vector.body, %entry
49    ret void
50  }
51
52  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
53  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
54  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
55  declare i32 @llvm.start.loop.iterations.i32(i32)
56  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
57
58...
59---
60name:            test
61alignment:       16
62tracksRegLiveness: true
63registers:       []
64liveins:
65  - { reg: '$r0', virtual-reg: '' }
66  - { reg: '$r1', virtual-reg: '' }
67  - { reg: '$r2', virtual-reg: '' }
68frameInfo:
69  stackSize:       8
70  offsetAdjustment: 0
71  maxAlignment:    4
72fixedStack:      []
73stack:
74  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
75      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
76      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
77  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
78      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
79      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
80callSites:       []
81constants:
82  - id:              0
83    value:           '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
84    alignment:       16
85    isTargetSpecific: false
86machineFunctionInfo: {}
87body:             |
88  ; CHECK-LABEL: name: test
89  ; CHECK: bb.0.entry:
90  ; CHECK:   successors: %bb.1(0x80000000)
91  ; CHECK:   liveins: $lr, $r0, $r1, $r2
92  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
93  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
94  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
95  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
96  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
97  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
98  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
99  ; CHECK:   t2IT 0, 8, implicit-def $itstate
100  ; CHECK:   frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
101  ; CHECK: bb.1.vector.ph:
102  ; CHECK:   successors: %bb.2(0x80000000)
103  ; CHECK:   liveins: $r0, $r1, $r2
104  ; CHECK:   renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
105  ; CHECK:   renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
106  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
107  ; CHECK:   renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
108  ; CHECK:   renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
109  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
110  ; CHECK: bb.2.vector.body:
111  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
112  ; CHECK:   liveins: $lr, $q0, $q1, $q2, $r0, $r1
113  ; CHECK:   MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr
114  ; CHECK:   renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4)
115  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4)
116  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
117  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
118  ; CHECK: bb.3.for.cond.cleanup:
119  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
120  ; CHECK: bb.4 (align 16):
121  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
122  bb.0.entry:
123    successors: %bb.1(0x80000000)
124    liveins: $r0, $r1, $r2, $lr
125
126    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
127    frame-setup CFI_INSTRUCTION def_cfa_offset 8
128    frame-setup CFI_INSTRUCTION offset $lr, -4
129    frame-setup CFI_INSTRUCTION offset $r7, -8
130    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
131    frame-setup CFI_INSTRUCTION def_cfa_register $r7
132    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
133    t2IT 0, 8, implicit-def $itstate
134    frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
135
136  bb.1.vector.ph:
137    successors: %bb.2(0x80000000)
138    liveins: $r0, $r1, $r2, $lr
139
140    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
141    renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
142    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
143    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
144    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
145    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
146    renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
147    renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool)
148    renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
149    renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
150    $lr = t2DoLoopStart renamable $lr
151
152  bb.2.vector.body:
153    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
154    liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
155
156    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
157    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
158    MVE_VPST 2, implicit $vpr
159    renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr
160    renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv35, align 4)
161    renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv12, align 4)
162    renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
163    renamable $lr = t2LoopDec killed renamable $lr, 1
164    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
165    tB %bb.3, 14 /* CC::al */, $noreg
166
167  bb.3.for.cond.cleanup:
168    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
169
170  bb.4 (align 16):
171    CONSTPOOL_ENTRY 0, %const.0, 16
172
173...
174