1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# A decent sized test to handle a matrix, with scalar and vector low-overhead loops. 5 6--- | 7 define dso_local arm_aapcs_vfpcc signext i16 @matrix_test(i32 %d, i32* nocapture %e, i16* nocapture readonly %k, i16* nocapture readonly %l) { 8 entry: 9 %cmp19.i = icmp sgt i32 %d, 0 10 br i1 %cmp19.i, label %for.body.i.preheader, label %c.exit.thread 11 12 for.body.i.preheader: ; preds = %entry 13 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %d) 14 br label %for.body.i 15 16 c.exit.thread: ; preds = %entry 17 %call169 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 0) 18 %conv270 = sext i16 %call169 to i32 19 br label %c.exit59 20 21 for.body.i: ; preds = %for.body.i, %for.body.i.preheader 22 %lsr.iv15 = phi i32* [ %e, %for.body.i.preheader ], [ %scevgep16, %for.body.i ] 23 %h.022.i = phi i16 [ %h.1.i, %for.body.i ], [ 0, %for.body.i.preheader ] 24 %f.020.i = phi i32 [ %f.1.i, %for.body.i ], [ undef, %for.body.i.preheader ] 25 %0 = phi i32 [ %start1, %for.body.i.preheader ], [ %2, %for.body.i ] 26 %1 = load i32, i32* %lsr.iv15, align 4 27 %add.i = add nsw i32 %1, %f.020.i 28 %cmp1.i = icmp sgt i32 %add.i, 0 29 %cmp3.i = icmp sgt i32 %1, 0 30 %f.1.i = select i1 %cmp1.i, i32 0, i32 %add.i 31 %narrow.i = and i1 %cmp3.i, %cmp1.i 32 %add6.i = zext i1 %narrow.i to i16 33 %h.1.i = add i16 %h.022.i, %add6.i 34 %scevgep16 = getelementptr i32, i32* %lsr.iv15, i32 1 35 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) 36 %3 = icmp ne i32 %2, 0 37 br i1 %3, label %for.body.i, label %c.exit 38 39 c.exit: ; preds = %for.body.i 40 %4 = icmp sgt i32 %d, 0 41 %phitmp = sext i16 %h.1.i to i32 42 %call1 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 %phitmp) 43 %conv2 = sext i16 %call1 to i32 44 br i1 %4, label %for.cond4.preheader.us.preheader, label %c.exit59 45 46 for.cond4.preheader.us.preheader: ; preds = %c.exit 47 %n.rnd.up = add i32 %d, 3 48 %n.vec = and i32 %n.rnd.up, -4 49 %5 = shl i32 %d, 1 50 %6 = add i32 %n.vec, -4 51 %7 = lshr i32 %6, 2 52 %8 = add nuw nsw i32 %7, 1 53 %9 = shl i32 %7, 2 54 %10 = sub i32 %d, %9 55 br label %for.cond4.preheader.us 56 57 for.cond4.preheader.us: ; preds = %middle.block, %for.cond4.preheader.us.preheader 58 %lsr.iv7 = phi i16* [ %28, %middle.block ], [ %k, %for.cond4.preheader.us.preheader ] 59 %i.064.us = phi i32 [ %inc15.us, %middle.block ], [ 0, %for.cond4.preheader.us.preheader ] 60 %arrayidx12.us = getelementptr inbounds i32, i32* %e, i32 %i.064.us 61 %arrayidx12.promoted.us = load i32, i32* %arrayidx12.us, align 4 62 %11 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx12.promoted.us, i32 0 63 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %8) 64 br label %vector.body 65 66 vector.body: ; preds = %vector.body, %for.cond4.preheader.us 67 %lsr.iv10 = phi i16* [ %scevgep11, %vector.body ], [ %lsr.iv7, %for.cond4.preheader.us ] 68 %lsr.iv4 = phi i16* [ %scevgep5, %vector.body ], [ %l, %for.cond4.preheader.us ] 69 %vec.phi = phi <4 x i32> [ %11, %for.cond4.preheader.us ], [ %19, %vector.body ] 70 %12 = phi i32 [ %start2, %for.cond4.preheader.us ], [ %20, %vector.body ] 71 %13 = phi i32 [ %d, %for.cond4.preheader.us ], [ %15, %vector.body ] 72 %lsr.iv1012 = bitcast i16* %lsr.iv10 to <4 x i16>* 73 %lsr.iv46 = bitcast i16* %lsr.iv4 to <4 x i16>* 74 %14 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %13) 75 %15 = sub i32 %13, 4 76 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1012, i32 2, <4 x i1> %14, <4 x i16> undef) 77 %16 = sext <4 x i16> %wide.masked.load to <4 x i32> 78 %wide.masked.load76 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv46, i32 2, <4 x i1> %14, <4 x i16> undef) 79 %17 = sext <4 x i16> %wide.masked.load76 to <4 x i32> 80 %18 = mul nsw <4 x i32> %17, %16 81 %19 = add <4 x i32> %18, %vec.phi 82 %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 4 83 %scevgep11 = getelementptr i16, i16* %lsr.iv10, i32 4 84 %20 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1) 85 %21 = icmp ne i32 %20, 0 86 br i1 %21, label %vector.body, label %middle.block 87 88 middle.block: ; preds = %vector.body 89 %vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ] 90 %.lcssa = phi <4 x i32> [ %19, %vector.body ] 91 %22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %10) 92 %23 = bitcast i16* %lsr.iv7 to i1* 93 %24 = select <4 x i1> %22, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa 94 %25 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %24) 95 %sunkaddr = mul i32 %i.064.us, 4 96 %26 = bitcast i32* %e to i8* 97 %sunkaddr17 = getelementptr inbounds i8, i8* %26, i32 %sunkaddr 98 %27 = bitcast i8* %sunkaddr17 to i32* 99 store i32 %25, i32* %27, align 4 100 %inc15.us = add nuw nsw i32 %i.064.us, 1 101 %scevgep9 = getelementptr i1, i1* %23, i32 %5 102 %28 = bitcast i1* %scevgep9 to i16* 103 %exitcond66 = icmp eq i32 %inc15.us, %d 104 br i1 %exitcond66, label %for.end16, label %for.cond4.preheader.us 105 106 for.end16: ; preds = %middle.block 107 %29 = icmp sgt i32 %d, 0 108 br i1 %29, label %for.body.i57.preheader, label %c.exit59 109 110 for.body.i57.preheader: ; preds = %for.end16 111 %start3 = call i32 @llvm.start.loop.iterations.i32(i32 %d) 112 br label %for.body.i57 113 114 for.body.i57: ; preds = %for.body.i57, %for.body.i57.preheader 115 %lsr.iv1 = phi i32* [ %e, %for.body.i57.preheader ], [ %scevgep, %for.body.i57 ] 116 %h.022.i44 = phi i16 [ %h.1.i54, %for.body.i57 ], [ 0, %for.body.i57.preheader ] 117 %f.020.i46 = phi i32 [ %f.1.i51, %for.body.i57 ], [ undef, %for.body.i57.preheader ] 118 %30 = phi i32 [ %start3, %for.body.i57.preheader ], [ %32, %for.body.i57 ] 119 %31 = load i32, i32* %lsr.iv1, align 4 120 %add.i48 = add nsw i32 %31, %f.020.i46 121 %cmp1.i49 = icmp sgt i32 %add.i48, 0 122 %cmp3.i50 = icmp sgt i32 %31, 0 123 %f.1.i51 = select i1 %cmp1.i49, i32 0, i32 %add.i48 124 %narrow.i52 = and i1 %cmp3.i50, %cmp1.i49 125 %add6.i53 = zext i1 %narrow.i52 to i16 126 %h.1.i54 = add i16 %h.022.i44, %add6.i53 127 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1 128 %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %30, i32 1) 129 %33 = icmp ne i32 %32, 0 130 br i1 %33, label %for.body.i57, label %c.exit59.loopexit 131 132 c.exit59.loopexit: ; preds = %for.body.i57 133 %phitmp67 = sext i16 %h.1.i54 to i32 134 br label %c.exit59 135 136 c.exit59: ; preds = %c.exit59.loopexit, %for.end16, %c.exit, %c.exit.thread 137 %conv27173 = phi i32 [ %conv2, %for.end16 ], [ %conv2, %c.exit59.loopexit ], [ %conv2, %c.exit ], [ %conv270, %c.exit.thread ] 138 %h.0.lcssa.i58 = phi i32 [ 0, %for.end16 ], [ %phitmp67, %c.exit59.loopexit ], [ 0, %c.exit ], [ 0, %c.exit.thread ] 139 %call19 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32, i32)*)(i32 %h.0.lcssa.i58, i32 %conv27173) 140 ret i16 %call19 141 } 142 declare dso_local arm_aapcs_vfpcc signext i16 @crc16(...) local_unnamed_addr #0 143 declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1 144 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2 145 declare i32 @llvm.start.loop.iterations.i32(i32) #3 146 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 147 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 148 149... 150--- 151name: matrix_test 152alignment: 2 153exposesReturnsTwice: false 154legalized: false 155regBankSelected: false 156selected: false 157failedISel: false 158tracksRegLiveness: true 159hasWinCFI: false 160registers: [] 161liveins: 162 - { reg: '$r0', virtual-reg: '' } 163 - { reg: '$r1', virtual-reg: '' } 164 - { reg: '$r2', virtual-reg: '' } 165 - { reg: '$r3', virtual-reg: '' } 166frameInfo: 167 isFrameAddressTaken: false 168 isReturnAddressTaken: false 169 hasStackMap: false 170 hasPatchPoint: false 171 stackSize: 32 172 offsetAdjustment: 0 173 maxAlignment: 4 174 adjustsStack: true 175 hasCalls: true 176 stackProtector: '' 177 maxCallFrameSize: 0 178 cvBytesOfCalleeSavedRegisters: 0 179 hasOpaqueSPAdjustment: false 180 hasVAStart: false 181 hasMustTailInVarArgFunc: false 182 localFrameSize: 0 183 savePoint: '' 184 restorePoint: '' 185fixedStack: [] 186stack: 187 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 188 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 189 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 190 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 191 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 192 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 193 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 194 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 195 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 196 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 197 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 198 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 199 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 200 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 201 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 202 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 203 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 204 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 205 - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 206 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 207 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 208 - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 209 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 210 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 211callSites: [] 212constants: [] 213machineFunctionInfo: {} 214body: | 215 ; CHECK-LABEL: name: matrix_test 216 ; CHECK: bb.0.entry: 217 ; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000) 218 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 219 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr 220 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32 221 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 222 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8 223 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -12 224 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -16 225 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -20 226 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24 227 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28 228 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32 229 ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 230 ; CHECK: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr 231 ; CHECK: bb.1.for.body.i.preheader: 232 ; CHECK: successors: %bb.2(0x80000000) 233 ; CHECK: liveins: $r0, $r1, $r2, $r3 234 ; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg 235 ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg 236 ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg 237 ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 238 ; CHECK: renamable $r2 = IMPLICIT_DEF 239 ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg 240 ; CHECK: $lr = t2DLS killed renamable $r0 241 ; CHECK: bb.2.for.body.i: 242 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 243 ; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10 244 ; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv15) 245 ; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg 246 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 247 ; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 248 ; CHECK: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 249 ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 250 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 251 ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg 252 ; CHECK: t2IT 12, 8, implicit-def $itstate 253 ; CHECK: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 254 ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg 255 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 256 ; CHECK: bb.3.c.exit: 257 ; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000) 258 ; CHECK: liveins: $r4, $r5, $r6, $r8, $r10 259 ; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg 260 ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 261 ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg 262 ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 263 ; CHECK: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 264 ; CHECK: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr 265 ; CHECK: bb.4.for.cond4.preheader.us.preheader: 266 ; CHECK: successors: %bb.5(0x80000000) 267 ; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12 268 ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg 269 ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg 270 ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg 271 ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg 272 ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg 273 ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 274 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 275 ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 276 ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg 277 ; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg 278 ; CHECK: bb.5.for.cond4.preheader.us: 279 ; CHECK: successors: %bb.6(0x80000000) 280 ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 281 ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.arrayidx12.us) 282 ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 283 ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg 284 ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg 285 ; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg 286 ; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg 287 ; CHECK: $lr = t2DLS renamable $r0 288 ; CHECK: bb.6.vector.body: 289 ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000) 290 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 291 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 292 ; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2 293 ; CHECK: MVE_VPST 4, implicit $vpr 294 ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1012, align 2) 295 ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv46, align 2) 296 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 297 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1 298 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1 299 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6 300 ; CHECK: bb.7.middle.block: 301 ; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000) 302 ; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 303 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg 304 ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg 305 ; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr 306 ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg 307 ; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg 308 ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store 4 into %ir.27) 309 ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg 310 ; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr 311 ; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr 312 ; CHECK: bb.8.for.end16: 313 ; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000) 314 ; CHECK: liveins: $lr, $r4, $r12 315 ; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 316 ; CHECK: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr 317 ; CHECK: bb.9.for.body.i57.preheader: 318 ; CHECK: successors: %bb.10(0x80000000) 319 ; CHECK: liveins: $lr, $r4, $r12 320 ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 321 ; CHECK: renamable $r1 = IMPLICIT_DEF 322 ; CHECK: $lr = t2DLS killed renamable $lr 323 ; CHECK: bb.10.for.body.i57: 324 ; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000) 325 ; CHECK: liveins: $lr, $r0, $r1, $r4, $r12 326 ; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv1) 327 ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg 328 ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 329 ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 330 ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 331 ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 332 ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 333 ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg 334 ; CHECK: t2IT 12, 8, implicit-def $itstate 335 ; CHECK: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate 336 ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg 337 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10 338 ; CHECK: bb.11.c.exit59.loopexit: 339 ; CHECK: successors: %bb.14(0x80000000) 340 ; CHECK: liveins: $r0, $r12 341 ; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg 342 ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg 343 ; CHECK: bb.12.c.exit.thread: 344 ; CHECK: successors: %bb.14(0x80000000) 345 ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 346 ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 347 ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 348 ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg 349 ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg 350 ; CHECK: bb.13: 351 ; CHECK: successors: %bb.14(0x80000000) 352 ; CHECK: liveins: $r12 353 ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 354 ; CHECK: bb.14.c.exit59: 355 ; CHECK: liveins: $r7, $r12 356 ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg 357 ; CHECK: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg 358 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr 359 ; CHECK: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1 360 bb.0.entry: 361 successors: %bb.1(0x50000000), %bb.12(0x30000000) 362 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr 363 364 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr 365 frame-setup CFI_INSTRUCTION def_cfa_offset 32 366 frame-setup CFI_INSTRUCTION offset $lr, -4 367 frame-setup CFI_INSTRUCTION offset $r10, -8 368 frame-setup CFI_INSTRUCTION offset $r9, -12 369 frame-setup CFI_INSTRUCTION offset $r8, -16 370 frame-setup CFI_INSTRUCTION offset $r7, -20 371 frame-setup CFI_INSTRUCTION offset $r6, -24 372 frame-setup CFI_INSTRUCTION offset $r5, -28 373 frame-setup CFI_INSTRUCTION offset $r4, -32 374 tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr 375 t2Bcc %bb.12, 11, killed $cpsr 376 377 bb.1.for.body.i.preheader: 378 successors: %bb.2(0x80000000) 379 liveins: $r0, $r1, $r2, $r3 380 381 $r5 = tMOVr killed $r2, 14, $noreg 382 $r8 = tMOVr killed $r3, 14, $noreg 383 $r4 = tMOVr $r1, 14, $noreg 384 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg 385 renamable $r2 = IMPLICIT_DEF 386 $r10 = tMOVr $r0, 14, $noreg 387 $lr = tMOVr $r0, 14, $noreg 388 $lr = t2DoLoopStart killed renamable $r0 389 390 bb.2.for.body.i: 391 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 392 liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10 393 394 renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.lsr.iv15) 395 renamable $lr = t2LoopDec killed renamable $lr, 1 396 renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg 397 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 398 renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 399 tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr 400 renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 401 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 402 renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg 403 t2IT 12, 8, implicit-def $itstate 404 $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 405 renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg 406 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 407 tB %bb.3, 14, $noreg 408 409 bb.3.c.exit: 410 successors: %bb.4(0x50000000), %bb.14(0x30000000) 411 liveins: $r4, $r5, $r6, $r8, $r10 412 413 renamable $r0 = tSXTH killed renamable $r6, 14, $noreg 414 tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 415 $r12 = tMOVr killed $r0, 14, $noreg 416 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg 417 t2CMPri $r10, 1, 14, $noreg, implicit-def $cpsr 418 tBcc %bb.14, 11, killed $cpsr 419 420 bb.4.for.cond4.preheader.us.preheader: 421 successors: %bb.5(0x80000000) 422 liveins: $r4, $r5, $r7, $r8, $r10, $r12 423 424 renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg 425 $lr = tMOVr $r10, 14, $noreg 426 renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg 427 renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg 428 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg 429 renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg 430 renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 431 renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg 432 renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg 433 renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg 434 435 bb.5.for.cond4.preheader.us: 436 successors: %bb.6(0x80000000) 437 liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 438 439 renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load 4 from %ir.arrayidx12.us) 440 $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 441 $r2 = tMOVr killed $lr, 14, $noreg 442 renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg 443 $r6 = tMOVr $r5, 14, $noreg 444 $r1 = tMOVr $r8, 14, $noreg 445 $lr = tMOVr $r0, 14, $noreg 446 $lr = t2DoLoopStart renamable $r0 447 448 bb.6.vector.body: 449 successors: %bb.6(0x7c000000), %bb.7(0x04000000) 450 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 451 452 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 453 $q2 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q2 454 MVE_VPST 4, implicit $vpr 455 renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1012, align 2) 456 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv46, align 2) 457 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 458 renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1 459 renamable $lr = t2LoopDec killed renamable $lr, 1 460 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1 461 t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr 462 tB %bb.7, 14, $noreg 463 464 bb.7.middle.block: 465 successors: %bb.8(0x04000000), %bb.5(0x7c000000) 466 liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 467 468 renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg 469 renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg 470 renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr 471 $lr = tMOVr $r10, 14, $noreg 472 renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg 473 t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store 4 into %ir.27) 474 renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg 475 tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr 476 tBcc %bb.5, 1, killed $cpsr 477 478 bb.8.for.end16: 479 successors: %bb.9(0x50000000), %bb.13(0x30000000) 480 liveins: $lr, $r4, $r12 481 482 t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr 483 tBcc %bb.13, 11, killed $cpsr 484 485 bb.9.for.body.i57.preheader: 486 successors: %bb.10(0x80000000) 487 liveins: $lr, $r4, $r12 488 489 renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg 490 renamable $r1 = IMPLICIT_DEF 491 $lr = t2DoLoopStart renamable $lr 492 493 bb.10.for.body.i57: 494 successors: %bb.10(0x7c000000), %bb.11(0x04000000) 495 liveins: $lr, $r0, $r1, $r4, $r12 496 497 renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14, $noreg :: (load 4 from %ir.lsr.iv1) 498 renamable $lr = t2LoopDec killed renamable $lr, 1 499 renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg 500 tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr 501 renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 502 tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr 503 renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 504 tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr 505 renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg 506 t2IT 12, 8, implicit-def $itstate 507 $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate 508 renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg 509 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr 510 tB %bb.11, 14, $noreg 511 512 bb.11.c.exit59.loopexit: 513 successors: %bb.14(0x80000000) 514 liveins: $r0, $r12 515 516 renamable $r7 = tSXTH killed renamable $r0, 14, $noreg 517 tB %bb.14, 14, $noreg 518 519 bb.12.c.exit.thread: 520 successors: %bb.14(0x80000000) 521 522 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 523 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg 524 tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 525 $r12 = tMOVr killed $r0, 14, $noreg 526 tB %bb.14, 14, $noreg 527 528 bb.13: 529 successors: %bb.14(0x80000000) 530 liveins: $r12 531 532 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg 533 534 bb.14.c.exit59: 535 liveins: $r7, $r12 536 537 $r0 = tMOVr killed $r7, 14, $noreg 538 $r1 = tMOVr killed $r12, 14, $noreg 539 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr 540 tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1 541 542... 543