1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3--- |
4  define dso_local arm_aapcs_vfpcc void @start_before_elems(i32* noalias nocapture %a, i8* nocapture readonly %b, i8* nocapture readonly %c, i32 %N) local_unnamed_addr #0 {
5  entry:
6    %div = lshr i32 %N, 1
7    %cmp9 = icmp eq i32 %div, 0
8    %0 = add nuw i32 %div, 3
9    %1 = lshr i32 %0, 2
10    %2 = shl nuw i32 %1, 2
11    %3 = add i32 %2, -4
12    %4 = lshr i32 %3, 2
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    br label %vector.body
19
20  vector.body:                                      ; preds = %vector.body, %vector.ph
21    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
22    %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
23    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
24    %7 = phi i32 [ %div, %vector.ph ], [ %9, %vector.body ]
25    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
26    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
27    %9 = sub i32 %7, 4
28    %scevgep4 = getelementptr i8, i8* %b, i32 %index
29    %scevgep45 = bitcast i8* %scevgep4 to <4 x i8>*
30    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %scevgep45, i32 1, <4 x i1> %8, <4 x i8> undef)
31    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
32    %scevgep2 = getelementptr i8, i8* %c, i32 %index
33    %scevgep23 = bitcast i8* %scevgep2 to <4 x i8>*
34    %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %scevgep23, i32 1, <4 x i1> %8, <4 x i8> undef)
35    %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
36    %12 = mul nuw nsw <4 x i32> %11, %10
37    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %12, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %8)
38    %index.next = add i32 %index, 4
39    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
40    %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
41    %14 = icmp ne i32 %13, 0
42    br i1 %14, label %vector.body, label %for.cond.cleanup
43
44  for.cond.cleanup:                                 ; preds = %vector.body, %entry
45    ret void
46  }
47  declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
48  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
49  declare i32 @llvm.start.loop.iterations.i32(i32)
50  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
51  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
52...
53---
54name:            start_before_elems
55alignment:       2
56exposesReturnsTwice: false
57legalized:       false
58regBankSelected: false
59selected:        false
60failedISel:      false
61tracksRegLiveness: true
62hasWinCFI:       false
63registers:       []
64liveins:
65  - { reg: '$r0', virtual-reg: '' }
66  - { reg: '$r1', virtual-reg: '' }
67  - { reg: '$r2', virtual-reg: '' }
68  - { reg: '$r3', virtual-reg: '' }
69frameInfo:
70  isFrameAddressTaken: false
71  isReturnAddressTaken: false
72  hasStackMap:     false
73  hasPatchPoint:   false
74  stackSize:       8
75  offsetAdjustment: 0
76  maxAlignment:    4
77  adjustsStack:    false
78  hasCalls:        false
79  stackProtector:  ''
80  maxCallFrameSize: 0
81  cvBytesOfCalleeSavedRegisters: 0
82  hasOpaqueSPAdjustment: false
83  hasVAStart:      false
84  hasMustTailInVarArgFunc: false
85  localFrameSize:  0
86  savePoint:       ''
87  restorePoint:    ''
88fixedStack:      []
89stack:
90  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
91      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
92      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
93  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
94      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
95      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
96callSites:       []
97constants:       []
98machineFunctionInfo: {}
99body:             |
100  ; CHECK-LABEL: name: start_before_elems
101  ; CHECK: bb.0.entry:
102  ; CHECK:   successors: %bb.1(0x80000000)
103  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
104  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
105  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
106  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
107  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
108  ; CHECK:   renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
109  ; CHECK:   t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
110  ; CHECK:   t2IT 0, 8, implicit-def $itstate
111  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
112  ; CHECK: bb.1.vector.ph:
113  ; CHECK:   successors: %bb.2(0x80000000)
114  ; CHECK:   liveins: $r0, $r1, $r2, $r3
115  ; CHECK:   renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg
116  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
117  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r12
118  ; CHECK: bb.2.vector.body:
119  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
120  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
121  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
122  ; CHECK:   renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
123  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
124  ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
125  ; CHECK:   renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
126  ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
127  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
128  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
129  ; CHECK: bb.3.for.cond.cleanup:
130  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
131  bb.0.entry:
132    successors: %bb.1(0x80000000)
133    liveins: $r0, $r1, $r2, $r3, $r4, $lr
134
135    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
136    frame-setup CFI_INSTRUCTION def_cfa_offset 8
137    frame-setup CFI_INSTRUCTION offset $lr, -4
138    frame-setup CFI_INSTRUCTION offset $r4, -8
139    renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
140    t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
141    t2IT 0, 8, implicit-def $itstate
142    tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
143
144  bb.1.vector.ph:
145    successors: %bb.2(0x80000000)
146    liveins: $r0, $r1, $r2, $r3, $r4, $lr
147
148    renamable $r12 = t2MOVi 3, 14, $noreg, $noreg
149    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
150    renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14, $noreg, $noreg
151    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
152    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
153    renamable $r5 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
154    renamable $r12 = t2LSRri killed renamable $r3, 1, 14, $noreg, $noreg
155    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
156    $lr = t2DoLoopStart renamable $r5
157    $lr = tMOVr killed $r5, 14, $noreg
158
159  bb.2.vector.body:
160    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
161    liveins: $lr, $r0, $r1, $r2, $r3, $r12
162
163    renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
164    renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
165    MVE_VPST 8, implicit $vpr
166    renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep45, align 1)
167    renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
168    renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
169    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
170    MVE_VPST 8, implicit $vpr
171    renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep23, align 1)
172    renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
173    MVE_VPST 8, implicit $vpr
174    renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
175    renamable $lr = t2LoopDec killed renamable $lr, 1
176    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
177    tB %bb.3, 14, $noreg
178
179  bb.3.for.cond.cleanup:
180    tPOP_RET 14, $noreg, def $r4, def $pc
181
182...
183