1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4# Test that, though the vctp operand is defined at the end of the block,
5# that the correct value is used for the dlstp.
6
7--- |
8  define dso_local arm_aapcs_vfpcc void @start_before_elems(i32* noalias nocapture %a, i8* nocapture readonly %b, i8* nocapture readonly %c, i32 %N) local_unnamed_addr #0 {
9  entry:
10    %div = lshr i32 %N, 1
11    %cmp9 = icmp eq i32 %div, 0
12    %0 = add nuw i32 %div, 3
13    %1 = lshr i32 %0, 2
14    %2 = shl nuw i32 %1, 2
15    %3 = add i32 %2, -4
16    %4 = lshr i32 %3, 2
17    %5 = add nuw nsw i32 %4, 1
18    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
19
20  vector.ph:                                        ; preds = %entry
21    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
22    br label %vector.body
23
24  vector.body:                                      ; preds = %vector.body, %vector.ph
25    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
26    %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
27    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
28    %7 = phi i32 [ %div, %vector.ph ], [ %9, %vector.body ]
29    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
30    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
31    %9 = sub i32 %7, 4
32    %scevgep4 = getelementptr i8, i8* %b, i32 %index
33    %scevgep45 = bitcast i8* %scevgep4 to <4 x i8>*
34    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %scevgep45, i32 1, <4 x i1> %8, <4 x i8> undef)
35    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
36    %scevgep2 = getelementptr i8, i8* %c, i32 %index
37    %scevgep23 = bitcast i8* %scevgep2 to <4 x i8>*
38    %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %scevgep23, i32 1, <4 x i1> %8, <4 x i8> undef)
39    %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
40    %12 = mul nuw nsw <4 x i32> %11, %10
41    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %12, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %8)
42    %index.next = add i32 %index, 4
43    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
44    %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
45    %14 = icmp ne i32 %13, 0
46    br i1 %14, label %vector.body, label %for.cond.cleanup
47
48  for.cond.cleanup:                                 ; preds = %vector.body, %entry
49    ret void
50  }
51  declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>) #1
52  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2
53  declare i32 @llvm.start.loop.iterations.i32(i32) #3
54  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
55  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
56
57...
58---
59name:            start_before_elems
60alignment:       2
61exposesReturnsTwice: false
62legalized:       false
63regBankSelected: false
64selected:        false
65failedISel:      false
66tracksRegLiveness: true
67hasWinCFI:       false
68registers:       []
69liveins:
70  - { reg: '$r0', virtual-reg: '' }
71  - { reg: '$r1', virtual-reg: '' }
72  - { reg: '$r2', virtual-reg: '' }
73  - { reg: '$r3', virtual-reg: '' }
74frameInfo:
75  isFrameAddressTaken: false
76  isReturnAddressTaken: false
77  hasStackMap:     false
78  hasPatchPoint:   false
79  stackSize:       8
80  offsetAdjustment: 0
81  maxAlignment:    4
82  adjustsStack:    false
83  hasCalls:        false
84  stackProtector:  ''
85  maxCallFrameSize: 0
86  cvBytesOfCalleeSavedRegisters: 0
87  hasOpaqueSPAdjustment: false
88  hasVAStart:      false
89  hasMustTailInVarArgFunc: false
90  localFrameSize:  0
91  savePoint:       ''
92  restorePoint:    ''
93fixedStack:      []
94stack:
95  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
96      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
97      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
98  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
99      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
100      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
101callSites:       []
102constants:       []
103machineFunctionInfo: {}
104body:             |
105  ; CHECK-LABEL: name: start_before_elems
106  ; CHECK: bb.0.entry:
107  ; CHECK:   successors: %bb.1(0x80000000)
108  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
109  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
110  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
111  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
112  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
113  ; CHECK:   renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
114  ; CHECK:   t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
115  ; CHECK:   t2IT 0, 8, implicit-def $itstate
116  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
117  ; CHECK: bb.1.vector.ph:
118  ; CHECK:   successors: %bb.2(0x80000000)
119  ; CHECK:   liveins: $r0, $r1, $r2, $r3
120  ; CHECK:   renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
121  ; CHECK:   renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
122  ; CHECK:   renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg
123  ; CHECK:   renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
124  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
125  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
126  ; CHECK:   $lr = t2DLS killed renamable $lr
127  ; CHECK:   $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
128  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
129  ; CHECK:   renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
130  ; CHECK: bb.2.vector.body:
131  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
132  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
133  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
134  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
135  ; CHECK:   MVE_VPST 8, implicit $vpr
136  ; CHECK:   renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep45, align 1)
137  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
138  ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
139  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
140  ; CHECK:   MVE_VPST 8, implicit $vpr
141  ; CHECK:   renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep23, align 1)
142  ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
143  ; CHECK:   MVE_VPST 8, implicit $vpr
144  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
145  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
146  ; CHECK: bb.3.for.cond.cleanup:
147  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
148  bb.0.entry:
149    successors: %bb.1(0x80000000)
150    liveins: $r0, $r1, $r2, $r3, $r4, $lr
151
152    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
153    frame-setup CFI_INSTRUCTION def_cfa_offset 8
154    frame-setup CFI_INSTRUCTION offset $lr, -4
155    frame-setup CFI_INSTRUCTION offset $r4, -8
156    renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
157    t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
158    t2IT 0, 8, implicit-def $itstate
159    tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
160
161  bb.1.vector.ph:
162    successors: %bb.2(0x80000000)
163    liveins: $r0, $r1, $r2, $r3, $r4, $lr
164
165    renamable $r12 = t2MOVi 3, 14, $noreg, $noreg
166    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
167    renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14, $noreg, $noreg
168    renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
169    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
170    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
171    $lr = t2DoLoopStart renamable $lr
172    $r12 = t2MOVr killed $r3, 14, $noreg, $noreg
173    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
174    renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg
175
176  bb.2.vector.body:
177    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
178    liveins: $lr, $r0, $r1, $r2, $r3, $r12
179
180    renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
181    renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
182    MVE_VPST 8, implicit $vpr
183    renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep45, align 1)
184    renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
185    renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
186    renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
187    MVE_VPST 8, implicit $vpr
188    renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep23, align 1)
189    renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
190    MVE_VPST 8, implicit $vpr
191    renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
192    renamable $lr = t2LoopDec killed renamable $lr, 1
193    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
194    tB %bb.3, 14, $noreg
195
196  bb.3.for.cond.cleanup:
197    tPOP_RET 14, $noreg, def $r4, def $pc
198
199...
200