1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* noalias nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) { 6 %5 = icmp eq i32 %3, 2 7 %6 = select i1 %5, i32 2, i32 4 8 %7 = icmp eq i32 %3, 4 9 %8 = select i1 %7, i32 1, i32 %6 10 %9 = shl i32 %2, %8 11 %10 = icmp eq i32 %9, 0 12 %11 = add i32 %9, 3 13 %12 = lshr i32 %11, 2 14 %13 = shl nuw i32 %12, 2 15 %14 = add i32 %13, -4 16 %15 = lshr i32 %14, 2 17 %16 = add nuw nsw i32 %15, 1 18 br i1 %10, label %34, label %17 19 20 17: ; preds = %4 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %16) 22 br label %18 23 24 18: ; preds = %18, %17 25 %19 = phi i32* [ %31, %18 ], [ %0, %17 ] 26 %20 = phi i32* [ %30, %18 ], [ %1, %17 ] 27 %21 = phi i32 [ %start, %17 ], [ %32, %18 ] 28 %22 = phi i32 [ %9, %17 ], [ %26, %18 ] 29 %23 = bitcast i32* %19 to <4 x i32>* 30 %24 = bitcast i32* %20 to <4 x i32>* 31 %25 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %22) 32 %26 = sub i32 %22, 4 33 %27 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %24, i32 4, <4 x i1> %25, <4 x i32> undef) 34 %28 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %23, i32 4, <4 x i1> %25, <4 x i32> undef) 35 %29 = mul nsw <4 x i32> %28, %27 36 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %29, <4 x i32>* %23, i32 4, <4 x i1> %25) 37 %30 = getelementptr i32, i32* %20, i32 4 38 %31 = getelementptr i32, i32* %19, i32 4 39 %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1) 40 %33 = icmp ne i32 %32, 0 41 br i1 %33, label %18, label %34 42 43 34: ; preds = %18, %4 44 ret void 45 } 46 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 47 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 48 declare i32 @llvm.start.loop.iterations.i32(i32) 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 50 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 51 52... 53--- 54name: multi_cond_iter_count 55alignment: 2 56tracksRegLiveness: true 57registers: [] 58liveins: 59 - { reg: '$r0', virtual-reg: '' } 60 - { reg: '$r1', virtual-reg: '' } 61 - { reg: '$r2', virtual-reg: '' } 62 - { reg: '$r3', virtual-reg: '' } 63frameInfo: 64 stackSize: 8 65 offsetAdjustment: 0 66 maxAlignment: 4 67fixedStack: [] 68stack: 69 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 70 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 71 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 72 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 73 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 74 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 75callSites: [] 76constants: [] 77machineFunctionInfo: {} 78body: | 79 ; CHECK-LABEL: name: multi_cond_iter_count 80 ; CHECK: bb.0 (%ir-block.4): 81 ; CHECK: successors: %bb.1(0x80000000) 82 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 83 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 84 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 85 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 86 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 87 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 88 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 89 ; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr 90 ; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg 91 ; CHECK: t2IT 1, 8, implicit-def $itstate 92 ; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 93 ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 94 ; CHECK: t2IT 0, 8, implicit-def $itstate 95 ; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 96 ; CHECK: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr 97 ; CHECK: t2IT 0, 8, implicit-def $itstate 98 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 99 ; CHECK: bb.1 (%ir-block.17): 100 ; CHECK: successors: %bb.2(0x80000000) 101 ; CHECK: liveins: $r0, $r1, $r2 102 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 103 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 104 ; CHECK: bb.2 (%ir-block.18): 105 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 106 ; CHECK: liveins: $lr, $r0, $r1, $r3 107 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg 108 ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg 109 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 110 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg 111 ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 112 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 113 ; CHECK: bb.3 (%ir-block.34): 114 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 115 bb.0 (%ir-block.4): 116 successors: %bb.1(0x80000000) 117 liveins: $r0, $r1, $r2, $r3, $lr 118 119 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 120 frame-setup CFI_INSTRUCTION def_cfa_offset 8 121 frame-setup CFI_INSTRUCTION offset $lr, -4 122 frame-setup CFI_INSTRUCTION offset $r7, -8 123 $r7 = frame-setup tMOVr $sp, 14, $noreg 124 frame-setup CFI_INSTRUCTION def_cfa_register $r7 125 tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr 126 $r12 = tMOVr $r3, 14, $noreg 127 t2IT 1, 8, implicit-def $itstate 128 $r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 129 tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr 130 t2IT 0, 8, implicit-def $itstate 131 $r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 132 renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr 133 t2IT 0, 8, implicit-def $itstate 134 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate 135 136 bb.1 (%ir-block.17): 137 successors: %bb.2(0x80000000) 138 liveins: $r0, $r1, $r2, $r3, $lr 139 140 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg 141 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg 142 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg 143 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg 144 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg 145 $r3 = tMOVr $r0, 14, $noreg 146 $lr = t2DoLoopStart renamable $lr 147 148 bb.2 (%ir-block.18): 149 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 150 liveins: $lr, $r0, $r1, $r2, $r3 151 152 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 153 MVE_VPST 4, implicit $vpr 154 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr 155 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr 156 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 157 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 158 MVE_VPST 8, implicit $vpr 159 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr 160 renamable $lr = t2LoopDec killed renamable $lr, 1 161 $r0 = tMOVr $r3, 14, $noreg 162 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 163 tB %bb.3, 14, $noreg 164 165 bb.3 (%ir-block.34): 166 tPOP_RET 14, $noreg, def $r7, def $pc 167 168... 169