1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
6  entry:
7    %cmp8 = icmp eq i32 %N, 0
8    br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
9
10  for.body.preheader:                               ; preds = %entry
11    %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
12    br label %for.body
13
14  for.cond.cleanup:                                 ; preds = %for.end, %entry
15    ret void
16
17  for.body:                                         ; preds = %for.end, %for.body.preheader
18    %lsr.iv4 = phi i32* [ %b, %for.body.preheader ], [ %scevgep5, %for.end ]
19    %lsr.iv2 = phi i32* [ %c, %for.body.preheader ], [ %scevgep3, %for.end ]
20    %lsr.iv1 = phi i32* [ %a, %for.body.preheader ], [ %scevgep, %for.end ]
21    %lsr.iv = phi i32 [ %start, %for.body.preheader ], [ %lsr.iv.next, %for.end ]
22    %size = call i32 @llvm.arm.space(i32 3072, i32 undef)
23    %0 = load i32, i32* %lsr.iv4, align 4
24    %1 = load i32, i32* %lsr.iv2, align 4
25    %mul = mul nsw i32 %1, %0
26    store i32 %mul, i32* %lsr.iv1, align 4
27    %cmp = icmp ne i32 %0, 0
28    br i1 %cmp, label %middle.block, label %for.end
29
30  middle.block:                                     ; preds = %for.body
31    %div = udiv i32 %1, %0
32    store i32 %div, i32* %lsr.iv1, align 4
33    %size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef)
34    br label %for.end
35
36  for.end:                                          ; preds = %middle.block, %for.body
37    %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
38    %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1
39    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
40    %lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
41    %exitcond = icmp eq i32 %lsr.iv.next, 0
42    br i1 %exitcond, label %for.cond.cleanup, label %for.body
43  }
44
45  ; Function Attrs: nounwind
46  declare i32 @llvm.arm.space(i32 immarg, i32) #0
47
48  ; Function Attrs: noduplicate nounwind
49  declare i32 @llvm.start.loop.iterations.i32(i32) #1
50
51  ; Function Attrs: noduplicate nounwind
52  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
53
54  ; Function Attrs: nounwind
55  declare void @llvm.stackprotector(i8*, i8**) #0
56
57  attributes #0 = { nounwind }
58  attributes #1 = { noduplicate nounwind }
59
60...
61---
62name:            size_limit
63alignment:       2
64exposesReturnsTwice: false
65legalized:       false
66regBankSelected: false
67selected:        false
68failedISel:      false
69tracksRegLiveness: true
70hasWinCFI:       false
71registers:       []
72liveins:
73  - { reg: '$r0', virtual-reg: '' }
74  - { reg: '$r1', virtual-reg: '' }
75  - { reg: '$r2', virtual-reg: '' }
76  - { reg: '$r3', virtual-reg: '' }
77frameInfo:
78  isFrameAddressTaken: false
79  isReturnAddressTaken: false
80  hasStackMap:     false
81  hasPatchPoint:   false
82  stackSize:       8
83  offsetAdjustment: 0
84  maxAlignment:    4
85  adjustsStack:    false
86  hasCalls:        false
87  stackProtector:  ''
88  maxCallFrameSize: 0
89  cvBytesOfCalleeSavedRegisters: 0
90  hasOpaqueSPAdjustment: false
91  hasVAStart:      false
92  hasMustTailInVarArgFunc: false
93  localFrameSize:  0
94  savePoint:       ''
95  restorePoint:    ''
96fixedStack:      []
97stack:
98  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
99      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
100      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
101  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
102      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
103      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
104callSites:       []
105constants:       []
106machineFunctionInfo: {}
107body:             |
108  ; CHECK-LABEL: name: size_limit
109  ; CHECK: bb.0.entry:
110  ; CHECK:   successors: %bb.1(0x80000000)
111  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
112  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
113  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
114  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
115  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
116  ; CHECK:   tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
117  ; CHECK:   t2IT 0, 8, implicit-def $itstate
118  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
119  ; CHECK: bb.1.for.body.preheader:
120  ; CHECK:   successors: %bb.2(0x80000000)
121  ; CHECK:   liveins: $r0, $r1, $r2, $r3
122  ; CHECK:   $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
123  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
124  ; CHECK: bb.2.for.end:
125  ; CHECK:   successors: %bb.5(0x04000000), %bb.3(0x7c000000)
126  ; CHECK:   liveins: $lr, $r0, $r1, $r2
127  ; CHECK:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
128  ; CHECK:   renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
129  ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
130  ; CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
131  ; CHECK:   tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
132  ; CHECK:   t2B %bb.5, 14 /* CC::al */, $noreg
133  ; CHECK: bb.3.for.body:
134  ; CHECK:   successors: %bb.4(0x50000000), %bb.2(0x30000000)
135  ; CHECK:   liveins: $lr, $r0, $r1, $r2
136  ; CHECK:   dead renamable $r3 = SPACE 3072, undef renamable $r0
137  ; CHECK:   renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv4)
138  ; CHECK:   renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.lsr.iv2)
139  ; CHECK:   tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
140  ; CHECK:   renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg
141  ; CHECK:   tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.lsr.iv1)
142  ; CHECK:   t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr
143  ; CHECK: bb.4.middle.block:
144  ; CHECK:   successors: %bb.2(0x80000000)
145  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
146  ; CHECK:   renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg
147  ; CHECK:   tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.lsr.iv1)
148  ; CHECK:   dead renamable $r3 = SPACE 1024, undef renamable $r0
149  ; CHECK:   t2B %bb.2, 14 /* CC::al */, $noreg
150  ; CHECK: bb.5.for.cond.cleanup:
151  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
152  bb.0.entry:
153    successors: %bb.1(0x80000000)
154    liveins: $r0, $r1, $r2, $r3, $r4, $lr
155
156    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
157    frame-setup CFI_INSTRUCTION def_cfa_offset 8
158    frame-setup CFI_INSTRUCTION offset $lr, -4
159    frame-setup CFI_INSTRUCTION offset $r4, -8
160    tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
161    t2IT 0, 8, implicit-def $itstate
162    tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
163
164  bb.1.for.body.preheader:
165    successors: %bb.2(0x80000000)
166    liveins: $r0, $r1, $r2, $r3, $r4, $lr
167
168    $lr = tMOVr $r3, 14, $noreg
169    $lr = t2DoLoopStart killed $r3
170    tB %bb.2, 14, $noreg
171
172  bb.2.for.end:
173    successors: %bb.5(0x04000000), %bb.3(0x7c000000)
174    liveins: $lr, $r0, $r1, $r2
175
176    renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
177    renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg
178    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
179    renamable $lr = t2LoopDec killed renamable $lr, 1
180    t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
181    t2B %bb.5, 14, $noreg
182
183  bb.3.for.body:
184    successors: %bb.4(0x50000000), %bb.2(0x30000000)
185    liveins: $lr, $r0, $r1, $r2
186
187    dead renamable $r3 = SPACE 3072, undef renamable $r0
188    renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4)
189    renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load 4 from %ir.lsr.iv2)
190    tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
191    renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg
192    tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1)
193    t2Bcc %bb.2, 0, killed $cpsr
194
195  bb.4.middle.block:
196    successors: %bb.2(0x80000000)
197    liveins: $lr, $r0, $r1, $r2, $r3, $r12
198
199    renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg
200    tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1)
201    dead renamable $r3 = SPACE 1024, undef renamable $r0
202    t2B %bb.2, 14, $noreg
203
204  bb.5.for.cond.cleanup:
205    tPOP_RET 14, $noreg, def $r4, def $pc
206
207...
208