1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-cp-islands %s -o - --verify-machineinstrs | FileCheck %s
3
4--- |
5  %struct.head_s = type { %struct.head_s*, %struct.data_s* }
6  %struct.data_s = type { i16, i16 }
7
8  define dso_local arm_aapcscc %struct.head_s* @search(%struct.head_s* readonly %list, %struct.data_s* nocapture readonly %info) local_unnamed_addr {
9  entry:
10    %idx = getelementptr inbounds %struct.data_s, %struct.data_s* %info, i32 0, i32 1
11    %tmp = load i16, i16* %idx, align 2
12    %cmp = icmp sgt i16 %tmp, -1
13    br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader
14
15  while.cond9.preheader:                            ; preds = %entry
16    %0 = icmp eq %struct.head_s* %list, null
17    br i1 %0, label %return, label %land.rhs11.lr.ph
18
19  land.rhs11.lr.ph:                                 ; preds = %while.cond9.preheader
20    %data16143 = bitcast %struct.data_s* %info to i16*
21    %tmp1 = load i16, i16* %data16143, align 2
22    %conv15 = sext i16 %tmp1 to i32
23    br label %land.rhs11
24
25  while.cond.preheader:                             ; preds = %entry
26    %1 = icmp eq %struct.head_s* %list, null
27    br i1 %1, label %return, label %land.rhs.preheader
28
29  land.rhs.preheader:                               ; preds = %while.cond.preheader
30    br label %land.rhs
31
32  while.body:                                       ; preds = %land.rhs
33    %next4 = bitcast %struct.head_s* %list.addr.033 to %struct.head_s**
34    %tmp4 = load %struct.head_s*, %struct.head_s** %next4, align 4
35    %tobool = icmp eq %struct.head_s* %tmp4, null
36    br i1 %tobool, label %return, label %land.rhs
37
38  land.rhs:                                         ; preds = %land.rhs.preheader, %while.body
39    %list.addr.033 = phi %struct.head_s* [ %tmp4, %while.body ], [ %list, %land.rhs.preheader ]
40    %info2 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.033, i32 0, i32 1
41    %tmp2 = load %struct.data_s*, %struct.data_s** %info2, align 4
42    %idx3 = getelementptr inbounds %struct.data_s, %struct.data_s* %tmp2, i32 0, i32 1
43    %tmp3 = load i16, i16* %idx3, align 2
44    %cmp7 = icmp eq i16 %tmp3, %tmp
45    br i1 %cmp7, label %return, label %while.body
46
47  while.body19:                                     ; preds = %land.rhs11
48    %next205 = bitcast %struct.head_s* %list.addr.136 to %struct.head_s**
49    %tmp8 = load %struct.head_s*, %struct.head_s** %next205, align 4
50    %tobool10 = icmp eq %struct.head_s* %tmp8, null
51    br i1 %tobool10, label %return, label %land.rhs11
52
53  land.rhs11:                                       ; preds = %while.body19, %land.rhs11.lr.ph
54    %list.addr.136 = phi %struct.head_s* [ %list, %land.rhs11.lr.ph ], [ %tmp8, %while.body19 ]
55    %info12 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.136, i32 0, i32 1
56    %tmp5 = load %struct.data_s*, %struct.data_s** %info12, align 4
57    %data166 = bitcast %struct.data_s* %tmp5 to i16*
58    %tmp6 = load i16, i16* %data166, align 2
59    %2 = and i16 %tmp6, 255
60    %and = zext i16 %2 to i32
61    %cmp16 = icmp eq i32 %and, %conv15
62    br i1 %cmp16, label %return, label %while.body19
63
64  return:                                           ; preds = %land.rhs11, %while.body19, %land.rhs, %while.body, %while.cond.preheader, %while.cond9.preheader
65    %retval.0 = phi %struct.head_s* [ null, %while.cond.preheader ], [ null, %while.cond9.preheader ], [ null, %while.body ], [ %list.addr.033, %land.rhs ], [ null, %while.body19 ], [ %list.addr.136, %land.rhs11 ]
66    ret %struct.head_s* %retval.0
67  }
68
69...
70---
71name:            search
72alignment:       2
73exposesReturnsTwice: false
74legalized:       false
75regBankSelected: false
76selected:        false
77failedISel:      false
78tracksRegLiveness: true
79hasWinCFI:       false
80registers:       []
81liveins:
82  - { reg: '$r0', virtual-reg: '' }
83  - { reg: '$r1', virtual-reg: '' }
84frameInfo:
85  isFrameAddressTaken: false
86  isReturnAddressTaken: false
87  hasStackMap:     false
88  hasPatchPoint:   false
89  stackSize:       0
90  offsetAdjustment: 0
91  maxAlignment:    1
92  adjustsStack:    false
93  hasCalls:        false
94  stackProtector:  ''
95  maxCallFrameSize: 0
96  cvBytesOfCalleeSavedRegisters: 0
97  hasOpaqueSPAdjustment: false
98  hasVAStart:      false
99  hasMustTailInVarArgFunc: false
100  localFrameSize:  0
101  savePoint:       ''
102  restorePoint:    ''
103fixedStack:      []
104stack:           []
105callSites:       []
106constants:       []
107machineFunctionInfo: {}
108body:             |
109  ; CHECK-LABEL: name: search
110  ; CHECK: bb.0.entry:
111  ; CHECK:   successors: %bb.1(0x50000000), %bb.6(0x30000000)
112  ; CHECK:   liveins: $r0, $r1
113  ; CHECK:   renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
114  ; CHECK:   t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
115  ; CHECK:   tBcc %bb.6, 13 /* CC::le */, killed $cpsr
116  ; CHECK: bb.1.while.cond.preheader:
117  ; CHECK:   successors: %bb.2(0x80000000)
118  ; CHECK:   liveins: $r0, $r2
119  ; CHECK:   tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
120  ; CHECK:   t2IT 0, 4, implicit-def $itstate
121  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
122  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
123  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
124  ; CHECK: bb.2:
125  ; CHECK:   successors: %bb.3(0x80000000)
126  ; CHECK:   liveins: $r0, $r2
127  ; CHECK:   renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
128  ; CHECK: bb.3.land.rhs:
129  ; CHECK:   successors: %bb.5(0x04000000), %bb.4(0x7c000000)
130  ; CHECK:   liveins: $r0, $r1
131  ; CHECK:   renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
132  ; CHECK:   renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
133  ; CHECK:   tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
134  ; CHECK:   tBcc %bb.5, 0 /* CC::eq */, killed $cpsr
135  ; CHECK: bb.4.while.body:
136  ; CHECK:   successors: %bb.3(0x80000000)
137  ; CHECK:   liveins: $r0, $r1
138  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
139  ; CHECK:   tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
140  ; CHECK:   t2IT 0, 4, implicit-def $itstate
141  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
142  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
143  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
144  ; CHECK: bb.5.return:
145  ; CHECK:   liveins: $r0
146  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
147  ; CHECK: bb.6.while.cond9.preheader:
148  ; CHECK:   successors: %bb.7(0x80000000)
149  ; CHECK:   liveins: $r0, $r1
150  ; CHECK:   tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
151  ; CHECK:   t2IT 0, 4, implicit-def $itstate
152  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
153  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
154  ; CHECK:   tB %bb.7, 14 /* CC::al */, $noreg
155  ; CHECK: bb.7.land.rhs11.lr.ph:
156  ; CHECK:   successors: %bb.8(0x80000000)
157  ; CHECK:   liveins: $r0, $r1
158  ; CHECK:   renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
159  ; CHECK: bb.8.land.rhs11:
160  ; CHECK:   successors: %bb.9(0x80000000)
161  ; CHECK:   liveins: $r0, $r1
162  ; CHECK:   renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
163  ; CHECK:   renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data166, align 2)
164  ; CHECK:   tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
165  ; CHECK:   t2IT 0, 8, implicit-def $itstate
166  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
167  ; CHECK:   tB %bb.9, 14 /* CC::al */, $noreg
168  ; CHECK: bb.9.while.body19:
169  ; CHECK:   successors: %bb.8(0x80000000)
170  ; CHECK:   liveins: $r0, $r1
171  ; CHECK:   renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next205)
172  ; CHECK:   tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
173  ; CHECK:   t2IT 0, 4, implicit-def $itstate
174  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
175  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
176  ; CHECK:   tB %bb.8, 14 /* CC::al */, $noreg
177  bb.0.entry:
178    successors: %bb.2(0x50000000), %bb.1(0x30000000)
179    liveins: $r0, $r1
180
181    renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
182    t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
183    t2Bcc %bb.1, 13 /* CC::le */, killed $cpsr
184
185  bb.2.while.cond.preheader:
186    successors: %bb.3(0x50000000)
187    liveins: $r0, $r2
188
189    tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
190    t2IT 0, 4, implicit-def $itstate
191    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
192    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
193    t2B %bb.3, 14 /* CC::al */, $noreg
194
195  bb.3:
196    successors: %bb.4(0x80000000)
197    liveins: $r0, $r2
198
199    renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
200
201  bb.4.land.rhs:
202    successors: %bb.9(0x04000000), %bb.5(0x7c000000)
203    liveins: $r0, $r1
204
205    renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
206    renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
207    tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
208    t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr
209
210  bb.5.while.body:
211    successors: %bb.4(0x7c000000)
212    liveins: $r0, $r1
213
214    renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
215    tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
216    t2IT 0, 4, implicit-def $itstate
217    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
218    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
219    t2B %bb.4, 14 /* CC::al */, $noreg
220
221  bb.9.return:
222    liveins: $r0
223
224    tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
225
226  bb.1.while.cond9.preheader:
227    successors: %bb.7(0x50000000)
228    liveins: $r0, $r1
229
230    tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
231    t2IT 0, 4, implicit-def $itstate
232    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
233    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
234    t2B %bb.7, 14 /* CC::al */, $noreg
235
236  bb.7.land.rhs11.lr.ph:
237    successors: %bb.8(0x80000000)
238    liveins: $r0, $r1
239
240    renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
241
242  bb.8.land.rhs11:
243    successors: %bb.6(0x80000000)
244    liveins: $r0, $r1
245
246    renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
247    renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data166, align 2)
248    tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
249    t2IT 0, 8, implicit-def $itstate
250    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
251    t2B %bb.6, 14 /* CC::al */, $noreg
252
253  bb.6.while.body19:
254    successors: %bb.8(0x7c000000)
255    liveins: $r0, $r1
256
257    renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next205)
258    tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
259    t2IT 0, 4, implicit-def $itstate
260    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
261    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
262    t2B %bb.8, 14 /* CC::al */, $noreg
263
264...
265