1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3--- |
4  define dso_local i32 @no_vpsel_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
5  entry:
6    %cmp9 = icmp eq i32 %N, 0
7    %tmp = add i32 %N, 3
8    %tmp1 = lshr i32 %tmp, 2
9    %tmp2 = shl nuw i32 %tmp1, 2
10    %tmp3 = add i32 %tmp2, -4
11    %tmp4 = lshr i32 %tmp3, 2
12    %tmp5 = add nuw nsw i32 %tmp4, 1
13    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
14
15  vector.ph:                                        ; preds = %entry
16    %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)
17    br label %vector.body
18
19  vector.body:                                      ; preds = %vector.body, %vector.ph
20    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
21    %lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
22    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
23    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]
24    %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]
25    %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
26    %lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
27    %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)
28    %tmp9 = sub i32 %tmp7, 4
29    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
30    %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
31    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
32    %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
33    %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10
34    %tmp13 = add <4 x i32> %tmp12, %vec.phi
35    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
36    %scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
37    %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
38    %tmp15 = icmp ne i32 %tmp14, 0
39    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
40    br i1 %tmp15, label %vector.body, label %middle.block
41
42  middle.block:                                     ; preds = %vector.body
43    %tmp16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp13)
44    br label %for.cond.cleanup
45
46  for.cond.cleanup:                                 ; preds = %middle.block, %entry
47    %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp16, %middle.block ]
48    ret i32 %res.0.lcssa
49  }
50  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
51  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
52  declare i32 @llvm.start.loop.iterations.i32(i32) #3
53  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
54  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
55
56...
57---
58name:            no_vpsel_liveout
59alignment:       2
60exposesReturnsTwice: false
61legalized:       false
62regBankSelected: false
63selected:        false
64failedISel:      false
65tracksRegLiveness: true
66hasWinCFI:       false
67registers:       []
68liveins:
69  - { reg: '$r0', virtual-reg: '' }
70  - { reg: '$r1', virtual-reg: '' }
71  - { reg: '$r2', virtual-reg: '' }
72frameInfo:
73  isFrameAddressTaken: false
74  isReturnAddressTaken: false
75  hasStackMap:     false
76  hasPatchPoint:   false
77  stackSize:       8
78  offsetAdjustment: 0
79  maxAlignment:    4
80  adjustsStack:    false
81  hasCalls:        false
82  stackProtector:  ''
83  maxCallFrameSize: 0
84  cvBytesOfCalleeSavedRegisters: 0
85  hasOpaqueSPAdjustment: false
86  hasVAStart:      false
87  hasMustTailInVarArgFunc: false
88  localFrameSize:  0
89  savePoint:       ''
90  restorePoint:    ''
91fixedStack:      []
92stack:
93  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
94      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
95      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
96  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
97      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
98      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
99callSites:       []
100constants:       []
101machineFunctionInfo: {}
102body:             |
103  ; CHECK-LABEL: name: no_vpsel_liveout
104  ; CHECK: bb.0.entry:
105  ; CHECK:   successors: %bb.1(0x80000000)
106  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
107  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
108  ; CHECK:   t2IT 0, 4, implicit-def $itstate
109  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
110  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
111  ; CHECK: bb.1.vector.ph:
112  ; CHECK:   successors: %bb.2(0x80000000)
113  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
114  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
115  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
116  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
117  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
118  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
119  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
120  ; CHECK: bb.2.vector.body:
121  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
122  ; CHECK:   liveins: $lr, $q0, $r0, $r1
123  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2)
124  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv1820, align 2)
125  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
126  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
127  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
128  ; CHECK: bb.3.middle.block:
129  ; CHECK:   liveins: $q0
130  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
131  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
132  bb.0.entry:
133    successors: %bb.1(0x80000000)
134    liveins: $r0, $r1, $r2, $lr, $r7
135
136    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
137    t2IT 0, 4, implicit-def $itstate
138    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
139    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
140
141  bb.1.vector.ph:
142    successors: %bb.2(0x80000000)
143    liveins: $r0, $r1, $r2, $lr, $r7
144
145    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
146    frame-setup CFI_INSTRUCTION def_cfa_offset 8
147    frame-setup CFI_INSTRUCTION offset $lr, -4
148    frame-setup CFI_INSTRUCTION offset $r7, -8
149    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
150    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
151    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
152    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
153    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
154    renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
155    $lr = t2DoLoopStart renamable $r12
156    $r3 = tMOVr killed $r12, 14, $noreg
157
158  bb.2.vector.body:
159    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
160    liveins: $q0, $r0, $r1, $r2, $r3
161
162    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
163    MVE_VPST 4, implicit $vpr
164    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
165    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
166    $lr = tMOVr $r3, 14, $noreg
167    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
168    renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
169    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
170    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
171    renamable $lr = t2LoopDec killed renamable $lr, 1
172    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
173    tB %bb.3, 14, $noreg
174
175  bb.3.middle.block:
176    liveins: $q0
177
178    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
179    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
180
181...
182