1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
3
4--- |
5  define dso_local arm_aapcs_vfpcc void @non_masked_store(i8* noalias nocapture %res, i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
6  entry:
7    %cmp10 = icmp eq i32 %N, 0
8    %0 = add i32 %N, 15
9    %1 = lshr i32 %0, 4
10    %2 = shl nuw i32 %1, 4
11    %3 = add i32 %2, -16
12    %4 = lshr i32 %3, 4
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp10, label %for.cond.cleanup, label %vector.ph
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    br label %vector.body
19
20  vector.body:                                      ; preds = %vector.body, %vector.ph
21    %lsr.iv19 = phi i8* [ %scevgep20, %vector.body ], [ %res, %vector.ph ]
22    %lsr.iv16 = phi i8* [ %scevgep17, %vector.body ], [ %b, %vector.ph ]
23    %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
24    %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]
25    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
26    %lsr.iv1921 = bitcast i8* %lsr.iv19 to <16 x i8>*
27    %lsr.iv1618 = bitcast i8* %lsr.iv16 to <16 x i8>*
28    %lsr.iv15 = bitcast i8* %lsr.iv to <16 x i8>*
29    %8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)
30    %9 = sub i32 %7, 16
31    %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv15, i32 1, <16 x i1> %8, <16 x i8> undef)
32    %wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv1618, i32 1, <16 x i1> %8, <16 x i8> undef)
33    %10 = add <16 x i8> %wide.masked.load14, %wide.masked.load
34    store <16 x i8> %10, <16 x i8>* %lsr.iv1921
35    %scevgep = getelementptr i8, i8* %lsr.iv, i32 16
36    %scevgep17 = getelementptr i8, i8* %lsr.iv16, i32 16
37    %scevgep20 = getelementptr i8, i8* %lsr.iv19, i32 16
38    %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
39    %12 = icmp ne i32 %11, 0
40    br i1 %12, label %vector.body, label %for.cond.cleanup
41
42  for.cond.cleanup:                                 ; preds = %vector.body, %entry
43    ret void
44  }
45
46  declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
47  declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
48  declare i32 @llvm.start.loop.iterations.i32(i32)
49  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
50  declare <16 x i1> @llvm.arm.mve.vctp8(i32)
51
52...
53---
54name:            non_masked_store
55alignment:       2
56exposesReturnsTwice: false
57legalized:       false
58regBankSelected: false
59selected:        false
60failedISel:      false
61tracksRegLiveness: true
62hasWinCFI:       false
63registers:       []
64liveins:
65  - { reg: '$r0', virtual-reg: '' }
66  - { reg: '$r1', virtual-reg: '' }
67  - { reg: '$r2', virtual-reg: '' }
68  - { reg: '$r3', virtual-reg: '' }
69frameInfo:
70  isFrameAddressTaken: false
71  isReturnAddressTaken: false
72  hasStackMap:     false
73  hasPatchPoint:   false
74  stackSize:       8
75  offsetAdjustment: 0
76  maxAlignment:    4
77  adjustsStack:    false
78  hasCalls:        false
79  stackProtector:  ''
80  maxCallFrameSize: 0
81  cvBytesOfCalleeSavedRegisters: 0
82  hasOpaqueSPAdjustment: false
83  hasVAStart:      false
84  hasMustTailInVarArgFunc: false
85  localFrameSize:  0
86  savePoint:       ''
87  restorePoint:    ''
88fixedStack:      []
89stack:
90  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
91      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
92      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
93  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
94      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
95      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
96callSites:       []
97constants:       []
98machineFunctionInfo: {}
99body:             |
100  ; CHECK-LABEL: name: non_masked_store
101  ; CHECK: bb.0.entry:
102  ; CHECK:   successors: %bb.1(0x80000000)
103  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
104  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
105  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
106  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
107  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
108  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
109  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
110  ; CHECK:   tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
111  ; CHECK:   t2IT 0, 8, implicit-def $itstate
112  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
113  ; CHECK: bb.1.vector.ph:
114  ; CHECK:   successors: %bb.2(0x80000000)
115  ; CHECK:   liveins: $r0, $r1, $r2, $r3
116  ; CHECK:   renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
117  ; CHECK:   renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
118  ; CHECK:   renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg
119  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
120  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
121  ; CHECK:   $lr = t2DLS killed renamable $lr
122  ; CHECK: bb.2.vector.body:
123  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
124  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
125  ; CHECK:   renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
126  ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
127  ; CHECK:   MVE_VPST 4, implicit $vpr
128  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1)
129  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1)
130  ; CHECK:   renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
131  ; CHECK:   renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1)
132  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
133  ; CHECK: bb.3.for.cond.cleanup:
134  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
135  bb.0.entry:
136    successors: %bb.1(0x80000000)
137    liveins: $r0, $r1, $r2, $r3, $lr
138
139    frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
140    frame-setup CFI_INSTRUCTION def_cfa_offset 8
141    frame-setup CFI_INSTRUCTION offset $lr, -4
142    frame-setup CFI_INSTRUCTION offset $r7, -8
143    $r7 = frame-setup tMOVr $sp, 14, $noreg
144    frame-setup CFI_INSTRUCTION def_cfa_register $r7
145    tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
146    t2IT 0, 8, implicit-def $itstate
147    tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
148
149  bb.1.vector.ph:
150    successors: %bb.2(0x80000000)
151    liveins: $r0, $r1, $r2, $r3, $lr
152
153    renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg
154    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
155    renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg
156    renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg
157    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg
158    $lr = t2DoLoopStart renamable $lr
159
160  bb.2.vector.body:
161    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
162    liveins: $lr, $r0, $r1, $r2, $r3
163
164    renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
165    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
166    MVE_VPST 4, implicit $vpr
167    renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1)
168    renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1)
169    renamable $lr = t2LoopDec killed renamable $lr, 1
170    renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
171    renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1)
172    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
173    tB %bb.3, 14, $noreg
174
175  bb.3.for.cond.cleanup:
176    tPOP_RET 14, $noreg, def $r7, def $pc
177
178...
179