1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4--- |
5  define dso_local arm_aapcs_vfpcc i32 @mul_var_i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
6  entry:
7    %cmp9.not = icmp eq i32 %N, 0
8    %0 = add i32 %N, 3
9    %1 = lshr i32 %0, 2
10    %2 = shl nuw i32 %1, 2
11    %3 = add i32 %2, -4
12    %4 = lshr i32 %3, 2
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    br label %vector.body
19
20  vector.body:                                      ; preds = %vector.body, %vector.ph
21    %lsr.iv14 = phi i8* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
22    %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
23    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
24    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
25    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
26    %lsr.iv13 = bitcast i8* %lsr.iv to <4 x i8>*
27    %lsr.iv1416 = bitcast i8* %lsr.iv14 to <4 x i8>*
28    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
29    %9 = sub i32 %7, 4
30    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv13, i32 1, <4 x i1> %8, <4 x i8> undef)
31    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
32    %wide.masked.load12 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv1416, i32 1, <4 x i1> %8, <4 x i8> undef)
33    %11 = zext <4 x i8> %wide.masked.load12 to <4 x i32>
34    %12 = mul nuw nsw <4 x i32> %11, %10
35    %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
36    %14 = add <4 x i32> %vec.phi, %13
37    %scevgep = getelementptr i8, i8* %lsr.iv, i32 4
38    %scevgep15 = getelementptr i8, i8* %lsr.iv14, i32 4
39    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
40    %16 = icmp ne i32 %15, 0
41    br i1 %16, label %vector.body, label %middle.block
42
43  middle.block:                                     ; preds = %vector.body
44    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
45    br label %for.cond.cleanup
46
47  for.cond.cleanup:                                 ; preds = %middle.block, %entry
48    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
49    ret i32 %res.0.lcssa
50  }
51
52  define dso_local arm_aapcs_vfpcc i32 @add_var_i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
53  entry:
54    %cmp10.not = icmp eq i32 %N, 0
55    %0 = add i32 %N, 3
56    %1 = lshr i32 %0, 2
57    %2 = shl nuw i32 %1, 2
58    %3 = add i32 %2, -4
59    %4 = lshr i32 %3, 2
60    %5 = add nuw nsw i32 %4, 1
61    br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
62
63  vector.ph:                                        ; preds = %entry
64    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
65    br label %vector.body
66
67  vector.body:                                      ; preds = %vector.body, %vector.ph
68    %lsr.iv15 = phi i8* [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
69    %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
70    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
71    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
72    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
73    %lsr.iv14 = bitcast i8* %lsr.iv to <4 x i8>*
74    %lsr.iv1517 = bitcast i8* %lsr.iv15 to <4 x i8>*
75    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
76    %9 = sub i32 %7, 4
77    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv14, i32 1, <4 x i1> %8, <4 x i8> undef)
78    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
79    %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv1517, i32 1, <4 x i1> %8, <4 x i8> undef)
80    %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
81    %12 = add <4 x i32> %vec.phi, %10
82    %13 = add <4 x i32> %12, %11
83    %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
84    %scevgep = getelementptr i8, i8* %lsr.iv, i32 4
85    %scevgep16 = getelementptr i8, i8* %lsr.iv15, i32 4
86    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
87    %16 = icmp ne i32 %15, 0
88    br i1 %16, label %vector.body, label %middle.block
89
90  middle.block:                                     ; preds = %vector.body
91    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
92    br label %for.cond.cleanup
93
94  for.cond.cleanup:                                 ; preds = %middle.block, %entry
95    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
96    ret i32 %res.0.lcssa
97  }
98
99  define dso_local arm_aapcs_vfpcc i32 @mul_var_i16(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) {
100  entry:
101    %cmp9.not = icmp eq i32 %N, 0
102    %0 = add i32 %N, 3
103    %1 = lshr i32 %0, 2
104    %2 = shl nuw i32 %1, 2
105    %3 = add i32 %2, -4
106    %4 = lshr i32 %3, 2
107    %5 = add nuw nsw i32 %4, 1
108    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
109
110  vector.ph:                                        ; preds = %entry
111    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
112    br label %vector.body
113
114  vector.body:                                      ; preds = %vector.body, %vector.ph
115    %lsr.iv14 = phi i16* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
116    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
117    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
118    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
119    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
120    %lsr.iv13 = bitcast i16* %lsr.iv to <4 x i16>*
121    %lsr.iv1416 = bitcast i16* %lsr.iv14 to <4 x i16>*
122    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
123    %9 = sub i32 %7, 4
124    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv13, i32 2, <4 x i1> %8, <4 x i16> undef)
125    %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
126    %wide.masked.load12 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1416, i32 2, <4 x i1> %8, <4 x i16> undef)
127    %11 = sext <4 x i16> %wide.masked.load12 to <4 x i32>
128    %12 = mul nsw <4 x i32> %11, %10
129    %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
130    %14 = add <4 x i32> %vec.phi, %13
131    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
132    %scevgep15 = getelementptr i16, i16* %lsr.iv14, i32 4
133    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
134    %16 = icmp ne i32 %15, 0
135    br i1 %16, label %vector.body, label %middle.block
136
137  middle.block:                                     ; preds = %vector.body
138    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
139    br label %for.cond.cleanup
140
141  for.cond.cleanup:                                 ; preds = %middle.block, %entry
142    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
143    ret i32 %res.0.lcssa
144  }
145
146  define dso_local arm_aapcs_vfpcc i32 @add_var_i16(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) {
147  entry:
148    %cmp10.not = icmp eq i32 %N, 0
149    %0 = add i32 %N, 3
150    %1 = lshr i32 %0, 2
151    %2 = shl nuw i32 %1, 2
152    %3 = add i32 %2, -4
153    %4 = lshr i32 %3, 2
154    %5 = add nuw nsw i32 %4, 1
155    br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
156
157  vector.ph:                                        ; preds = %entry
158    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
159    br label %vector.body
160
161  vector.body:                                      ; preds = %vector.body, %vector.ph
162    %lsr.iv15 = phi i16* [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
163    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
164    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
165    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
166    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
167    %lsr.iv14 = bitcast i16* %lsr.iv to <4 x i16>*
168    %lsr.iv1517 = bitcast i16* %lsr.iv15 to <4 x i16>*
169    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
170    %9 = sub i32 %7, 4
171    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv14, i32 2, <4 x i1> %8, <4 x i16> undef)
172    %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
173    %wide.masked.load13 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1517, i32 2, <4 x i1> %8, <4 x i16> undef)
174    %11 = sext <4 x i16> %wide.masked.load13 to <4 x i32>
175    %12 = add <4 x i32> %vec.phi, %10
176    %13 = add <4 x i32> %12, %11
177    %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
178    %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
179    %scevgep16 = getelementptr i16, i16* %lsr.iv15, i32 4
180    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
181    %16 = icmp ne i32 %15, 0
182    br i1 %16, label %vector.body, label %middle.block
183
184  middle.block:                                     ; preds = %vector.body
185    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
186    br label %for.cond.cleanup
187
188  for.cond.cleanup:                                 ; preds = %middle.block, %entry
189    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
190    ret i32 %res.0.lcssa
191  }
192
193  ; Function Attrs: norecurse nounwind readonly
194  define dso_local arm_aapcs_vfpcc i32 @mul_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
195  entry:
196    %cmp8.not = icmp eq i32 %N, 0
197    %0 = add i32 %N, 3
198    %1 = lshr i32 %0, 2
199    %2 = shl nuw i32 %1, 2
200    %3 = add i32 %2, -4
201    %4 = lshr i32 %3, 2
202    %5 = add nuw nsw i32 %4, 1
203    br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph
204
205  vector.ph:                                        ; preds = %entry
206    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
207    br label %vector.body
208
209  vector.body:                                      ; preds = %vector.body, %vector.ph
210    %lsr.iv13 = phi i32* [ %scevgep14, %vector.body ], [ %b, %vector.ph ]
211    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
212    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
213    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
214    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
215    %lsr.iv12 = bitcast i32* %lsr.iv to <4 x i32>*
216    %lsr.iv1315 = bitcast i32* %lsr.iv13 to <4 x i32>*
217    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
218    %9 = sub i32 %7, 4
219    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)
220    %wide.masked.load11 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1315, i32 4, <4 x i1> %8, <4 x i32> undef)
221    %10 = mul nsw <4 x i32> %wide.masked.load11, %wide.masked.load
222    %11 = select <4 x i1> %8, <4 x i32> %10, <4 x i32> zeroinitializer
223    %12 = add <4 x i32> %vec.phi, %11
224    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
225    %scevgep14 = getelementptr i32, i32* %lsr.iv13, i32 4
226    %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
227    %14 = icmp ne i32 %13, 0
228    br i1 %14, label %vector.body, label %middle.block
229
230  middle.block:                                     ; preds = %vector.body
231    %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
232    br label %for.cond.cleanup
233
234  for.cond.cleanup:                                 ; preds = %middle.block, %entry
235    %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
236    ret i32 %res.0.lcssa
237  }
238
239  ; Function Attrs: norecurse nounwind readonly
240  define dso_local arm_aapcs_vfpcc i32 @add_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
241  entry:
242    %cmp9.not = icmp eq i32 %N, 0
243    %0 = add i32 %N, 3
244    %1 = lshr i32 %0, 2
245    %2 = shl nuw i32 %1, 2
246    %3 = add i32 %2, -4
247    %4 = lshr i32 %3, 2
248    %5 = add nuw nsw i32 %4, 1
249    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
250
251  vector.ph:                                        ; preds = %entry
252    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
253    br label %vector.body
254
255  vector.body:                                      ; preds = %vector.body, %vector.ph
256    %lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
257    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
258    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
259    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
260    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
261    %lsr.iv13 = bitcast i32* %lsr.iv to <4 x i32>*
262    %lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
263    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
264    %9 = sub i32 %7, 4
265    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)
266    %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)
267    %10 = add <4 x i32> %wide.masked.load, %vec.phi
268    %11 = add <4 x i32> %10, %wide.masked.load12
269    %12 = select <4 x i1> %8, <4 x i32> %11, <4 x i32> %vec.phi
270    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
271    %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4
272    %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
273    %14 = icmp ne i32 %13, 0
274    br i1 %14, label %vector.body, label %middle.block
275
276  middle.block:                                     ; preds = %vector.body
277    %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
278    br label %for.cond.cleanup
279
280  for.cond.cleanup:                                 ; preds = %middle.block, %entry
281    %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
282    ret i32 %res.0.lcssa
283  }
284
285  declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
286  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
287  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
288  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
289  declare i32 @llvm.start.loop.iterations.i32(i32)
290  declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
291  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
292
293...
294---
295name:            mul_var_i8
296alignment:       2
297tracksRegLiveness: true
298registers:       []
299liveins:
300  - { reg: '$r0', virtual-reg: '' }
301  - { reg: '$r1', virtual-reg: '' }
302  - { reg: '$r2', virtual-reg: '' }
303frameInfo:
304  stackSize:       8
305  offsetAdjustment: 0
306  maxAlignment:    4
307fixedStack:      []
308stack:
309  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
310      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
311      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
312  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
313      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
314      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
315callSites:       []
316constants:       []
317machineFunctionInfo: {}
318body:             |
319  ; CHECK-LABEL: name: mul_var_i8
320  ; CHECK: bb.0.entry:
321  ; CHECK:   successors: %bb.1(0x80000000)
322  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
323  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
324  ; CHECK:   t2IT 0, 4, implicit-def $itstate
325  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
326  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
327  ; CHECK: bb.1.vector.ph:
328  ; CHECK:   successors: %bb.2(0x80000000)
329  ; CHECK:   liveins: $lr, $r0, $r1, $r2
330  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
331  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
332  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
333  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
334  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
335  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
336  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
337  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
338  ; CHECK: bb.2.vector.body (align 4):
339  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
340  ; CHECK:   liveins: $lr, $q0, $r0, $r1
341  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load 4 from %ir.lsr.iv13, align 1)
342  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load 4 from %ir.lsr.iv1416, align 1)
343  ; CHECK:   renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
344  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
345  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
346  ; CHECK: bb.3.middle.block:
347  ; CHECK:   liveins: $q0
348  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
349  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
350  bb.0.entry:
351    successors: %bb.1(0x50000000)
352    liveins: $r0, $r1, $r2, $lr
353
354    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
355    t2IT 0, 4, implicit-def $itstate
356    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
357    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
358
359  bb.1.vector.ph:
360    successors: %bb.2(0x80000000)
361    liveins: $r0, $r1, $r2, $lr
362
363    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
364    frame-setup CFI_INSTRUCTION def_cfa_offset 8
365    frame-setup CFI_INSTRUCTION offset $lr, -4
366    frame-setup CFI_INSTRUCTION offset $r7, -8
367    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
368    frame-setup CFI_INSTRUCTION def_cfa_register $r7
369    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
370    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
371    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
372    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
373    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
374    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
375    $lr = t2DoLoopStart renamable $lr
376
377  bb.2.vector.body (align 4):
378    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
379    liveins: $lr, $q0, $r0, $r1, $r2
380
381    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
382    MVE_VPST 4, implicit $vpr
383    renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv13, align 1)
384    renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv1416, align 1)
385    renamable $lr = t2LoopDec killed renamable $lr, 1
386    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
387    renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
388    MVE_VPST 8, implicit $vpr
389    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
390    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
391    tB %bb.3, 14 /* CC::al */, $noreg
392
393  bb.3.middle.block:
394    liveins: $q0
395
396    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
397    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
398
399...
400---
401name:            add_var_i8
402alignment:       2
403tracksRegLiveness: true
404registers:       []
405liveins:
406  - { reg: '$r0', virtual-reg: '' }
407  - { reg: '$r1', virtual-reg: '' }
408  - { reg: '$r2', virtual-reg: '' }
409frameInfo:
410  stackSize:       8
411  offsetAdjustment: 0
412  maxAlignment:    4
413fixedStack:      []
414stack:
415  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
416      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
417      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
418  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
419      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
420      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
421callSites:       []
422constants:       []
423machineFunctionInfo: {}
424body:             |
425  ; CHECK-LABEL: name: add_var_i8
426  ; CHECK: bb.0.entry:
427  ; CHECK:   successors: %bb.1(0x80000000)
428  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
429  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
430  ; CHECK:   t2IT 0, 4, implicit-def $itstate
431  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
432  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
433  ; CHECK: bb.1.vector.ph:
434  ; CHECK:   successors: %bb.2(0x80000000)
435  ; CHECK:   liveins: $lr, $r0, $r1, $r2
436  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
437  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
438  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
439  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
440  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
441  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
442  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
443  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
444  ; CHECK: bb.2.vector.body (align 4):
445  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
446  ; CHECK:   liveins: $lr, $q0, $r0, $r1
447  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load 4 from %ir.lsr.iv14, align 1)
448  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load 4 from %ir.lsr.iv1517, align 1)
449  ; CHECK:   renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
450  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
451  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
452  ; CHECK: bb.3.middle.block:
453  ; CHECK:   liveins: $q0
454  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
455  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
456  bb.0.entry:
457    successors: %bb.1(0x50000000)
458    liveins: $r0, $r1, $r2, $lr
459
460    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
461    t2IT 0, 4, implicit-def $itstate
462    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
463    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
464
465  bb.1.vector.ph:
466    successors: %bb.2(0x80000000)
467    liveins: $r0, $r1, $r2, $lr
468
469    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
470    frame-setup CFI_INSTRUCTION def_cfa_offset 8
471    frame-setup CFI_INSTRUCTION offset $lr, -4
472    frame-setup CFI_INSTRUCTION offset $r7, -8
473    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
474    frame-setup CFI_INSTRUCTION def_cfa_register $r7
475    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
476    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
477    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
478    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
479    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
480    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
481    $lr = t2DoLoopStart renamable $lr
482
483  bb.2.vector.body (align 4):
484    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
485    liveins: $lr, $q0, $r0, $r1, $r2
486
487    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
488    MVE_VPST 4, implicit $vpr
489    renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv14, align 1)
490    renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv1517, align 1)
491    renamable $lr = t2LoopDec killed renamable $lr, 1
492    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
493    renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
494    MVE_VPST 8, implicit $vpr
495    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
496    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
497    tB %bb.3, 14 /* CC::al */, $noreg
498
499  bb.3.middle.block:
500    liveins: $q0
501
502    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
503    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
504
505...
506---
507name:            mul_var_i16
508alignment:       2
509exposesReturnsTwice: false
510tracksRegLiveness: true
511registers:       []
512liveins:
513  - { reg: '$r0', virtual-reg: '' }
514  - { reg: '$r1', virtual-reg: '' }
515  - { reg: '$r2', virtual-reg: '' }
516frameInfo:
517  stackSize:       8
518  offsetAdjustment: 0
519  maxAlignment:    4
520fixedStack:      []
521stack:
522  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
523      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
524      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
525  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
526      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
527      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
528callSites:       []
529constants:       []
530machineFunctionInfo: {}
531body:             |
532  ; CHECK-LABEL: name: mul_var_i16
533  ; CHECK: bb.0.entry:
534  ; CHECK:   successors: %bb.1(0x80000000)
535  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
536  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
537  ; CHECK:   t2IT 0, 4, implicit-def $itstate
538  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
539  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
540  ; CHECK: bb.1.vector.ph:
541  ; CHECK:   successors: %bb.2(0x80000000)
542  ; CHECK:   liveins: $lr, $r0, $r1, $r2
543  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
544  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
545  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
546  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
547  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
548  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
549  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
550  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
551  ; CHECK: bb.2.vector.body (align 4):
552  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
553  ; CHECK:   liveins: $lr, $q0, $r0, $r1
554  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv13, align 2)
555  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1416, align 2)
556  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
557  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
558  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
559  ; CHECK: bb.3.middle.block:
560  ; CHECK:   liveins: $q0
561  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
562  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
563  bb.0.entry:
564    successors: %bb.1(0x50000000)
565    liveins: $r0, $r1, $r2, $lr
566
567    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
568    t2IT 0, 4, implicit-def $itstate
569    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
570    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
571
572  bb.1.vector.ph:
573    successors: %bb.2(0x80000000)
574    liveins: $r0, $r1, $r2, $lr
575
576    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
577    frame-setup CFI_INSTRUCTION def_cfa_offset 8
578    frame-setup CFI_INSTRUCTION offset $lr, -4
579    frame-setup CFI_INSTRUCTION offset $r7, -8
580    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
581    frame-setup CFI_INSTRUCTION def_cfa_register $r7
582    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
583    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
584    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
585    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
586    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
587    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
588    $lr = t2DoLoopStart renamable $lr
589
590  bb.2.vector.body (align 4):
591    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
592    liveins: $lr, $q0, $r0, $r1, $r2
593
594    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
595    MVE_VPST 4, implicit $vpr
596    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv13, align 2)
597    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1416, align 2)
598    renamable $lr = t2LoopDec killed renamable $lr, 1
599    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
600    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
601    MVE_VPST 8, implicit $vpr
602    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
603    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
604    tB %bb.3, 14 /* CC::al */, $noreg
605
606  bb.3.middle.block:
607    liveins: $q0
608
609    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
610    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
611
612...
613---
614name:            add_var_i16
615alignment:       2
616tracksRegLiveness: true
617registers:       []
618liveins:
619  - { reg: '$r0', virtual-reg: '' }
620  - { reg: '$r1', virtual-reg: '' }
621  - { reg: '$r2', virtual-reg: '' }
622frameInfo:
623  stackSize:       8
624  offsetAdjustment: 0
625  maxAlignment:    4
626fixedStack:      []
627stack:
628  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
629      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
630      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
631  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
632      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
633      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
634callSites:       []
635constants:       []
636machineFunctionInfo: {}
637body:             |
638  ; CHECK-LABEL: name: add_var_i16
639  ; CHECK: bb.0.entry:
640  ; CHECK:   successors: %bb.1(0x80000000)
641  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
642  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
643  ; CHECK:   t2IT 0, 4, implicit-def $itstate
644  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
645  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
646  ; CHECK: bb.1.vector.ph:
647  ; CHECK:   successors: %bb.2(0x80000000)
648  ; CHECK:   liveins: $lr, $r0, $r1, $r2
649  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
650  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
651  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
652  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
653  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
654  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
655  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
656  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
657  ; CHECK: bb.2.vector.body (align 4):
658  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
659  ; CHECK:   liveins: $lr, $q0, $r0, $r1
660  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv14, align 2)
661  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1517, align 2)
662  ; CHECK:   renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
663  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
664  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
665  ; CHECK: bb.3.middle.block:
666  ; CHECK:   liveins: $q0
667  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
668  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
669  bb.0.entry:
670    successors: %bb.1(0x50000000)
671    liveins: $r0, $r1, $r2, $lr
672
673    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
674    t2IT 0, 4, implicit-def $itstate
675    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
676    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
677
678  bb.1.vector.ph:
679    successors: %bb.2(0x80000000)
680    liveins: $r0, $r1, $r2, $lr
681
682    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
683    frame-setup CFI_INSTRUCTION def_cfa_offset 8
684    frame-setup CFI_INSTRUCTION offset $lr, -4
685    frame-setup CFI_INSTRUCTION offset $r7, -8
686    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
687    frame-setup CFI_INSTRUCTION def_cfa_register $r7
688    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
689    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
690    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
691    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
692    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
693    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
694    $lr = t2DoLoopStart renamable $lr
695
696  bb.2.vector.body (align 4):
697    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
698    liveins: $lr, $q0, $r0, $r1, $r2
699
700    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
701    MVE_VPST 4, implicit $vpr
702    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv14, align 2)
703    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1517, align 2)
704    renamable $lr = t2LoopDec killed renamable $lr, 1
705    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
706    renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
707    MVE_VPST 8, implicit $vpr
708    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
709    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
710    tB %bb.3, 14 /* CC::al */, $noreg
711
712  bb.3.middle.block:
713    liveins: $q0
714
715    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
716    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
717
718...
719---
720name:            mul_var_i32
721alignment:       2
722tracksRegLiveness: true
723registers:       []
724liveins:
725  - { reg: '$r0', virtual-reg: '' }
726  - { reg: '$r1', virtual-reg: '' }
727  - { reg: '$r2', virtual-reg: '' }
728frameInfo:
729  stackSize:       8
730  offsetAdjustment: 0
731  maxAlignment:    4
732fixedStack:      []
733stack:
734  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
735      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
736      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
737  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
738      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
739      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
740callSites:       []
741constants:       []
742machineFunctionInfo: {}
743body:             |
744  ; CHECK-LABEL: name: mul_var_i32
745  ; CHECK: bb.0.entry:
746  ; CHECK:   successors: %bb.1(0x80000000)
747  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
748  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
749  ; CHECK:   t2IT 0, 4, implicit-def $itstate
750  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
751  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
752  ; CHECK: bb.1.vector.ph:
753  ; CHECK:   successors: %bb.2(0x80000000)
754  ; CHECK:   liveins: $lr, $r0, $r1, $r2
755  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
756  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
757  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
758  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
759  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
760  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
761  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
762  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
763  ; CHECK: bb.2.vector.body (align 4):
764  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
765  ; CHECK:   liveins: $lr, $q0, $r0, $r1
766  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.lsr.iv12, align 4)
767  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1315, align 4)
768  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
769  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
770  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
771  ; CHECK: bb.3.middle.block:
772  ; CHECK:   liveins: $q0
773  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
774  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
775  bb.0.entry:
776    successors: %bb.1(0x50000000)
777    liveins: $r0, $r1, $r2, $lr
778
779    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
780    t2IT 0, 4, implicit-def $itstate
781    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
782    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
783
784  bb.1.vector.ph:
785    successors: %bb.2(0x80000000)
786    liveins: $r0, $r1, $r2, $lr
787
788    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
789    frame-setup CFI_INSTRUCTION def_cfa_offset 8
790    frame-setup CFI_INSTRUCTION offset $lr, -4
791    frame-setup CFI_INSTRUCTION offset $r7, -8
792    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
793    frame-setup CFI_INSTRUCTION def_cfa_register $r7
794    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
795    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
796    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
797    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
798    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
799    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
800    $lr = t2DoLoopStart renamable $lr
801
802  bb.2.vector.body (align 4):
803    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
804    liveins: $lr, $q0, $r0, $r1, $r2
805
806    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
807    MVE_VPST 4, implicit $vpr
808    renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv12, align 4)
809    renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1315, align 4)
810    renamable $lr = t2LoopDec killed renamable $lr, 1
811    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
812    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
813    MVE_VPST 8, implicit $vpr
814    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
815    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
816    tB %bb.3, 14 /* CC::al */, $noreg
817
818  bb.3.middle.block:
819    liveins: $q0
820
821    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
822    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
823
824...
825---
826name:            add_var_i32
827alignment:       2
828tracksRegLiveness: true
829registers:       []
830liveins:
831  - { reg: '$r0', virtual-reg: '' }
832  - { reg: '$r1', virtual-reg: '' }
833  - { reg: '$r2', virtual-reg: '' }
834frameInfo:
835  stackSize:       8
836  offsetAdjustment: 0
837  maxAlignment:    4
838fixedStack:      []
839stack:
840  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
841      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
842      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
843  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
844      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
845      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
846callSites:       []
847constants:       []
848machineFunctionInfo: {}
849body:             |
850  ; CHECK-LABEL: name: add_var_i32
851  ; CHECK: bb.0.entry:
852  ; CHECK:   successors: %bb.1(0x80000000)
853  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
854  ; CHECK:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
855  ; CHECK:   t2IT 0, 4, implicit-def $itstate
856  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
857  ; CHECK:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
858  ; CHECK: bb.1.vector.ph:
859  ; CHECK:   successors: %bb.2(0x80000000)
860  ; CHECK:   liveins: $lr, $r0, $r1, $r2
861  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
862  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
863  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
864  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
865  ; CHECK:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
866  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
867  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
868  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
869  ; CHECK: bb.2.vector.body (align 4):
870  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
871  ; CHECK:   liveins: $lr, $q0, $r0, $r1
872  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
873  ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
874  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
875  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
876  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
877  ; CHECK: bb.3.middle.block:
878  ; CHECK:   liveins: $q0
879  ; CHECK:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
880  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
881  bb.0.entry:
882    successors: %bb.1(0x50000000)
883    liveins: $r0, $r1, $r2, $lr
884
885    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
886    t2IT 0, 4, implicit-def $itstate
887    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
888    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
889
890  bb.1.vector.ph:
891    successors: %bb.2(0x80000000)
892    liveins: $r0, $r1, $r2, $lr
893
894    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
895    frame-setup CFI_INSTRUCTION def_cfa_offset 8
896    frame-setup CFI_INSTRUCTION offset $lr, -4
897    frame-setup CFI_INSTRUCTION offset $r7, -8
898    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
899    frame-setup CFI_INSTRUCTION def_cfa_register $r7
900    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
901    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
902    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
903    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
904    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
905    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
906    $lr = t2DoLoopStart renamable $lr
907
908  bb.2.vector.body (align 4):
909    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
910    liveins: $lr, $q0, $r0, $r1, $r2
911
912    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
913    MVE_VPST 4, implicit $vpr
914    renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
915    renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
916    renamable $lr = t2LoopDec killed renamable $lr, 1
917    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
918    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
919    MVE_VPST 8, implicit $vpr
920    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
921    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
922    tB %bb.3, 14 /* CC::al */, $noreg
923
924  bb.3.middle.block:
925    liveins: $q0
926
927    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
928    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
929
930...
931