1# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
2
3# CHECK: while.body:
4# CHECK-NOT: t2DLS
5# CHECK-NOT: t2LEUpdate
6
7--- |
8  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
9  target triple = "thumbv8.1m.main"
10
11  define i32 @skip_spill(i32 %n) #0 {
12  entry:
13    %cmp6 = icmp eq i32 %n, 0
14    br i1 %cmp6, label %while.end, label %while.body.preheader
15
16  while.body.preheader:                             ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %n)
18    br label %while.body
19
20  while.body:                                       ; preds = %while.body, %while.body.preheader
21    %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
22    %0 = phi i32 [ %start, %while.body.preheader ], [ %1, %while.body ]
23    %call = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)()
24    %add = add nsw i32 %call, %res.07
25    %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
26    %2 = icmp ne i32 %1, 0
27    br i1 %2, label %while.body, label %while.end
28
29  while.end:                                        ; preds = %while.body, %entry
30    %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ]
31    ret i32 %res.0.lcssa
32  }
33
34  declare i32 @bar(...) local_unnamed_addr #0
35
36  declare i32 @llvm.start.loop.iterations.i32(i32) #1
37  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
38
39  attributes #0 = { "target-features"="+mve.fp" }
40  attributes #1 = { noduplicate nounwind }
41  attributes #2 = { nounwind }
42
43...
44---
45name:            skip_spill
46alignment:       2
47exposesReturnsTwice: false
48legalized:       false
49regBankSelected: false
50selected:        false
51failedISel:      false
52tracksRegLiveness: true
53hasWinCFI:       false
54registers:       []
55liveins:
56  - { reg: '$r0', virtual-reg: '' }
57frameInfo:
58  isFrameAddressTaken: false
59  isReturnAddressTaken: false
60  hasStackMap:     false
61  hasPatchPoint:   false
62  stackSize:       16
63  offsetAdjustment: 0
64  maxAlignment:    4
65  adjustsStack:    true
66  hasCalls:        true
67  stackProtector:  ''
68  maxCallFrameSize: 0
69  cvBytesOfCalleeSavedRegisters: 0
70  hasOpaqueSPAdjustment: false
71  hasVAStart:      false
72  hasMustTailInVarArgFunc: false
73  localFrameSize:  0
74  savePoint:       ''
75  restorePoint:    ''
76fixedStack:      []
77stack:
78  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
79      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
80      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
81  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
82      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
83      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
84  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
85      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
86      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
87  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
88      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
89      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
90callSites:       []
91constants:       []
92machineFunctionInfo: {}
93body:             |
94  bb.0.entry:
95    successors: %bb.4(0x30000000), %bb.1(0x50000000)
96    liveins: $r0, $r4, $r5, $r7, $lr
97
98    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
99    frame-setup CFI_INSTRUCTION def_cfa_offset 16
100    frame-setup CFI_INSTRUCTION offset $lr, -4
101    frame-setup CFI_INSTRUCTION offset $r7, -8
102    frame-setup CFI_INSTRUCTION offset $r5, -12
103    frame-setup CFI_INSTRUCTION offset $r4, -16
104    tCBZ $r0, %bb.4
105
106  bb.1.while.body.preheader:
107    successors: %bb.2(0x80000000)
108    liveins: $r0
109
110    $lr = tMOVr $r0, 14, $noreg
111    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
112    $lr = t2DoLoopStart killed $r0
113
114  bb.2.while.body:
115    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
116    liveins: $lr, $r4
117
118    $r5 = tMOVr killed $lr, 14, $noreg
119    tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
120    $lr = tMOVr killed $r5, 14, $noreg
121    renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
122    renamable $lr = t2LoopDec killed renamable $lr, 1
123    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
124    tB %bb.3, 14, $noreg
125
126  bb.3.while.end:
127    liveins: $r4
128
129    $r0 = tMOVr killed $r4, 14, $noreg
130    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
131
132  bb.4:
133    renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
134    $r0 = tMOVr killed $r4, 14, $noreg
135    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
136
137...
138