1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6  target triple = "thumbv8.1m.main"
7
8  define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 {
9  entry:
10    %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
11    br i1 %0, label %do.body.preheader, label %if.end
12
13  do.body.preheader:                                ; preds = %entry
14    %scevgep2 = getelementptr i32, i32* %a, i32 -1
15    %scevgep5 = getelementptr i32, i32* %b, i32 -1
16    br label %do.body
17
18  do.body:                                          ; preds = %do.body, %do.body.preheader
19    %lsr.iv6 = phi i32* [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ]
20    %lsr.iv = phi i32* [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ]
21    %1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ]
22    %scevgep = getelementptr i32, i32* %lsr.iv6, i32 1
23    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
24    %size = call i32 @llvm.arm.space(i32 4096, i32 undef)
25    %tmp = load i32, i32* %scevgep, align 4
26    store i32 %tmp, i32* %scevgep1, align 4
27    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
28    %3 = icmp ne i32 %2, 0
29    %scevgep3 = getelementptr i32, i32* %lsr.iv, i32 1
30    %scevgep7 = getelementptr i32, i32* %lsr.iv6, i32 1
31    br i1 %3, label %do.body, label %if.end
32
33  if.end:                                           ; preds = %do.body, %entry
34    ret void
35  }
36
37  ; Function Attrs: nounwind
38  declare i32 @llvm.arm.space(i32 immarg, i32) #1
39
40  ; Function Attrs: noduplicate nounwind
41  declare i1 @llvm.test.set.loop.iterations.i32(i32) #2
42
43  ; Function Attrs: noduplicate nounwind
44  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
45
46  attributes #0 = { "target-features"="+lob" }
47  attributes #1 = { nounwind }
48  attributes #2 = { noduplicate nounwind }
49
50...
51---
52name:            ne_trip_count
53alignment:       2
54exposesReturnsTwice: false
55legalized:       false
56regBankSelected: false
57selected:        false
58failedISel:      false
59tracksRegLiveness: true
60hasWinCFI:       false
61registers:       []
62liveins:
63  - { reg: '$r1', virtual-reg: '' }
64  - { reg: '$r2', virtual-reg: '' }
65  - { reg: '$r3', virtual-reg: '' }
66frameInfo:
67  isFrameAddressTaken: false
68  isReturnAddressTaken: false
69  hasStackMap:     false
70  hasPatchPoint:   false
71  stackSize:       8
72  offsetAdjustment: 0
73  maxAlignment:    4
74  adjustsStack:    false
75  hasCalls:        false
76  stackProtector:  ''
77  maxCallFrameSize: 0
78  cvBytesOfCalleeSavedRegisters: 0
79  hasOpaqueSPAdjustment: false
80  hasVAStart:      false
81  hasMustTailInVarArgFunc: false
82  localFrameSize:  0
83  savePoint:       ''
84  restorePoint:    ''
85fixedStack:      []
86stack:
87  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
88      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
89      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
90  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
91      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
92      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
93callSites:       []
94constants:       []
95machineFunctionInfo: {}
96body:             |
97  ; CHECK-LABEL: name: ne_trip_count
98  ; CHECK: bb.0.entry:
99  ; CHECK:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
100  ; CHECK:   liveins: $lr, $r1, $r2, $r3, $r7
101  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
102  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
103  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
104  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
105  ; CHECK:   t2CMPri $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
106  ; CHECK:   t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
107  ; CHECK:   tB %bb.1, 14 /* CC::al */, $noreg
108  ; CHECK: bb.1.do.body.preheader:
109  ; CHECK:   successors: %bb.2(0x80000000)
110  ; CHECK:   liveins: $r1, $r2, $r3
111  ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
112  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
113  ; CHECK:   $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
114  ; CHECK: bb.2.do.body:
115  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
116  ; CHECK:   liveins: $lr, $r0, $r1
117  ; CHECK:   dead renamable $r2 = SPACE 4096, undef renamable $r0
118  ; CHECK:   renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep)
119  ; CHECK:   early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
120  ; CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
121  ; CHECK:   t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
122  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
123  ; CHECK: bb.3.if.end:
124  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
125  bb.0.entry:
126    successors: %bb.1(0x40000000), %bb.3(0x40000000)
127    liveins: $r1, $r2, $r3, $r7, $lr
128
129    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
130    frame-setup CFI_INSTRUCTION def_cfa_offset 8
131    frame-setup CFI_INSTRUCTION offset $lr, -4
132    frame-setup CFI_INSTRUCTION offset $r7, -8
133    t2WhileLoopStart $r3, %bb.3, implicit-def dead $cpsr
134    tB %bb.1, 14, $noreg
135
136  bb.1.do.body.preheader:
137    successors: %bb.2(0x80000000)
138    liveins: $r1, $r2, $r3
139
140    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
141    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
142    $lr = tMOVr killed $r3, 14, $noreg
143
144  bb.2.do.body:
145    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
146    liveins: $lr, $r0, $r1
147
148    dead renamable $r2 = SPACE 4096, undef renamable $r0
149    renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep)
150    early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1)
151    renamable $lr = t2LoopDec killed renamable $lr, 1
152    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
153    tB %bb.3, 14, $noreg
154
155  bb.3.if.end:
156    tPOP_RET 14, $noreg, def $r7, def $pc
157
158...
159