1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  ; ModuleID = 'size-limit.ll'
6  source_filename = "size-limit.ll"
7  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
8  target triple = "thumbv8.1m.main"
9
10  define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
11  entry:
12    %cmp8 = icmp eq i32 %N, 0
13    br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
14
15  for.body.preheader:                               ; preds = %entry
16    %scevgep = getelementptr i32, i32* %a, i32 -1
17    %scevgep4 = getelementptr i32, i32* %c, i32 -1
18    %scevgep8 = getelementptr i32, i32* %b, i32 -1
19    %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
20    br label %for.body
21
22  for.cond.cleanup:                                 ; preds = %for.body, %entry
23    ret void
24
25  for.body:                                         ; preds = %for.body, %for.body.preheader
26    %lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
27    %lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
28    %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
29    %0 = phi i32 [ %start, %for.body.preheader ], [ %3, %for.body ]
30    %size = call i32 @llvm.arm.space(i32 4070, i32 undef)
31    %scevgep3 = getelementptr i32, i32* %lsr.iv9, i32 1
32    %1 = load i32, i32* %scevgep3, align 4
33    %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1
34    %2 = load i32, i32* %scevgep7, align 4
35    %mul = mul nsw i32 %2, %1
36    %scevgep11 = getelementptr i32, i32* %lsr.iv1, i32 1
37    store i32 %mul, i32* %scevgep11, align 4
38    %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
39    %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
40    %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
41    %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
42    %4 = icmp ne i32 %3, 0
43    br i1 %4, label %for.body, label %for.cond.cleanup
44  }
45
46  ; Function Attrs: nounwind
47  declare i32 @llvm.arm.space(i32 immarg, i32) #0
48
49  ; Function Attrs: noduplicate nounwind
50  declare i32 @llvm.start.loop.iterations.i32(i32) #1
51
52  ; Function Attrs: noduplicate nounwind
53  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
54
55  ; Function Attrs: nounwind
56  declare void @llvm.stackprotector(i8*, i8**) #0
57
58  attributes #0 = { nounwind }
59  attributes #1 = { noduplicate nounwind }
60
61...
62---
63name:            size_limit
64alignment:       2
65exposesReturnsTwice: false
66legalized:       false
67regBankSelected: false
68selected:        false
69failedISel:      false
70tracksRegLiveness: true
71hasWinCFI:       false
72registers:       []
73liveins:
74  - { reg: '$r0', virtual-reg: '' }
75  - { reg: '$r1', virtual-reg: '' }
76  - { reg: '$r2', virtual-reg: '' }
77  - { reg: '$r3', virtual-reg: '' }
78frameInfo:
79  isFrameAddressTaken: false
80  isReturnAddressTaken: false
81  hasStackMap:     false
82  hasPatchPoint:   false
83  stackSize:       8
84  offsetAdjustment: 0
85  maxAlignment:    4
86  adjustsStack:    false
87  hasCalls:        false
88  stackProtector:  ''
89  maxCallFrameSize: 0
90  cvBytesOfCalleeSavedRegisters: 0
91  hasOpaqueSPAdjustment: false
92  hasVAStart:      false
93  hasMustTailInVarArgFunc: false
94  localFrameSize:  0
95  savePoint:       ''
96  restorePoint:    ''
97fixedStack:      []
98stack:
99  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
100      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
101      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
102  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
103      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
104      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
105callSites:       []
106constants:       []
107machineFunctionInfo: {}
108body:             |
109  ; CHECK-LABEL: name: size_limit
110  ; CHECK: bb.0.entry:
111  ; CHECK:   successors: %bb.1(0x80000000)
112  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
113  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
114  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
115  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
116  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
117  ; CHECK:   tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
118  ; CHECK:   t2IT 0, 8, implicit-def $itstate
119  ; CHECK:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
120  ; CHECK: bb.1.for.body.preheader:
121  ; CHECK:   successors: %bb.2(0x80000000)
122  ; CHECK:   liveins: $r0, $r1, $r2, $r3
123  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
124  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
125  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
126  ; CHECK:   $lr = t2DLS killed $r3
127  ; CHECK: bb.2.for.body:
128  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
129  ; CHECK:   liveins: $lr, $r0, $r1, $r2
130  ; CHECK:   dead renamable $r3 = SPACE 4070, undef renamable $r0
131  ; CHECK:   renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
132  ; CHECK:   renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
133  ; CHECK:   renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg
134  ; CHECK:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep11)
135  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
136  ; CHECK: bb.3.for.cond.cleanup:
137  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
138  bb.0.entry:
139    successors: %bb.1(0x80000000)
140    liveins: $r0, $r1, $r2, $r3, $r7, $lr
141
142    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
143    frame-setup CFI_INSTRUCTION def_cfa_offset 8
144    frame-setup CFI_INSTRUCTION offset $lr, -4
145    frame-setup CFI_INSTRUCTION offset $r7, -8
146    tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
147    t2IT 0, 8, implicit-def $itstate
148    tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
149
150  bb.1.for.body.preheader:
151    successors: %bb.2(0x80000000)
152    liveins: $r0, $r1, $r2, $r3, $r7, $lr
153
154    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
155    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
156    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
157    $lr = tMOVr $r3, 14, $noreg
158    $lr = t2DoLoopStart killed $r3
159
160  bb.2.for.body:
161    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
162    liveins: $lr, $r0, $r1, $r2
163
164    dead renamable $r3 = SPACE 4070, undef renamable $r0
165    renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3)
166    renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
167    renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg
168    early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11)
169    renamable $lr = t2LoopDec killed renamable $lr, 1
170    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
171    tB %bb.3, 14, $noreg
172
173  bb.3.for.cond.cleanup:
174    tPOP_RET 14, $noreg, def $r7, def $pc
175
176...
177