1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define arm_aapcs_vfpcc void @test_vmvn(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c, i32 %elts, i32 %iters) #0 { 6 entry: 7 %cmp = icmp slt i32 %elts, 1 8 br i1 %cmp, label %exit, label %loop.ph 9 10 loop.ph: ; preds = %entry 11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters) 12 br label %loop.body 13 14 loop.body: ; preds = %loop.body, %loop.ph 15 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ] 16 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ] 17 %addr.a = phi <4 x i32>* [ %a, %loop.ph ], [ %addr.a.next, %loop.body ] 18 %addr.b = phi <4 x i32>* [ %b, %loop.ph ], [ %addr.b.next, %loop.body ] 19 %addr.c = phi <4 x i32>* [ %c, %loop.ph ], [ %addr.c.next, %loop.body ] 20 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count) 21 %elts.rem = sub i32 %count, 4 22 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef) 23 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef) 24 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1> 25 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16> 26 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %not, i32 15, i32 1, i32 0, i32 0, i32 0, i32 0) 27 %bitcast = bitcast <8 x i16> %shrn to <4 x i32> 28 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %bitcast, <4 x i32>* %addr.c, i32 4, <4 x i1> %pred) 29 %addr.a.next = getelementptr <4 x i32>, <4 x i32>* %addr.a, i32 1 30 %addr.b.next = getelementptr <4 x i32>, <4 x i32>* %addr.b, i32 1 31 %addr.c.next = getelementptr <4 x i32>, <4 x i32>* %addr.c, i32 1 32 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 33 %end = icmp ne i32 %loop.dec, 0 34 %lsr.iv.next = add i32 %lsr.iv, -1 35 br i1 %end, label %loop.body, label %exit 36 37 exit: ; preds = %loop.body, %entry 38 ret void 39 } 40 41 define arm_aapcs_vfpcc void @test_vorn(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c, i32 %elts, i32 %iters) #0 { 42 entry: 43 %cmp = icmp slt i32 %elts, 1 44 br i1 %cmp, label %exit, label %loop.ph 45 46 loop.ph: ; preds = %entry 47 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters) 48 br label %loop.body 49 50 loop.body: ; preds = %loop.body, %loop.ph 51 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ] 52 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ] 53 %addr.a = phi <4 x i32>* [ %a, %loop.ph ], [ %addr.a.next, %loop.body ] 54 %addr.b = phi <4 x i32>* [ %b, %loop.ph ], [ %addr.b.next, %loop.body ] 55 %addr.c = phi <4 x i32>* [ %c, %loop.ph ], [ %addr.c.next, %loop.body ] 56 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count) 57 %elts.rem = sub i32 %count, 4 58 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef) 59 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef) 60 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1> 61 %or = or <4 x i32> %not, %masked.load.a 62 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16> 63 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %or, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1) 64 %bitcast = bitcast <8 x i16> %shrn to <4 x i32> 65 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %bitcast, <4 x i32>* %addr.c, i32 4, <4 x i1> %pred) 66 %addr.a.next = getelementptr <4 x i32>, <4 x i32>* %addr.a, i32 1 67 %addr.b.next = getelementptr <4 x i32>, <4 x i32>* %addr.b, i32 1 68 %addr.c.next = getelementptr <4 x i32>, <4 x i32>* %addr.c, i32 1 69 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 70 %end = icmp ne i32 %loop.dec, 0 71 %lsr.iv.next = add i32 %lsr.iv, -1 72 br i1 %end, label %loop.body, label %exit 73 74 exit: ; preds = %loop.body, %entry 75 ret void 76 } 77 78 declare i32 @llvm.start.loop.iterations.i32(i32) 79 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 80 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 81 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 82 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 83 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) 84 85... 86--- 87name: test_vmvn 88alignment: 2 89tracksRegLiveness: true 90registers: [] 91liveins: 92 - { reg: '$r0', virtual-reg: '' } 93 - { reg: '$r1', virtual-reg: '' } 94 - { reg: '$r2', virtual-reg: '' } 95 - { reg: '$r3', virtual-reg: '' } 96frameInfo: 97 stackSize: 8 98 offsetAdjustment: 0 99 maxAlignment: 4 100fixedStack: 101 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 102 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 104stack: 105 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 106 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 107 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 108 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 109 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 110 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 111callSites: [] 112constants: [] 113machineFunctionInfo: {} 114body: | 115 ; CHECK-LABEL: name: test_vmvn 116 ; CHECK: bb.0.entry: 117 ; CHECK: successors: %bb.1(0x80000000) 118 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 119 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 120 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 121 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 122 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 123 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 124 ; CHECK: t2IT 11, 8, implicit-def $itstate 125 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 126 ; CHECK: bb.1.loop.ph: 127 ; CHECK: successors: %bb.2(0x80000000) 128 ; CHECK: liveins: $r0, $r1, $r2, $r3 129 ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) 130 ; CHECK: dead $lr = t2DLS renamable $r4 131 ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 132 ; CHECK: bb.2.loop.body: 133 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 134 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 135 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 136 ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 137 ; CHECK: MVE_VPST 4, implicit $vpr 138 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.addr.a, align 4) 139 ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.addr.b, align 4) 140 ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 141 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 142 ; CHECK: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, undef renamable $q1 143 ; CHECK: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg 144 ; CHECK: MVE_VPST 8, implicit $vpr 145 ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store 16 into %ir.addr.c, align 4) 146 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 147 ; CHECK: bb.3.exit: 148 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 149 bb.0.entry: 150 successors: %bb.1(0x80000000) 151 liveins: $r0, $r1, $r2, $r3, $r4, $lr 152 153 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 154 frame-setup CFI_INSTRUCTION def_cfa_offset 8 155 frame-setup CFI_INSTRUCTION offset $lr, -4 156 frame-setup CFI_INSTRUCTION offset $r4, -8 157 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 158 t2IT 11, 8, implicit-def $itstate 159 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 160 161 bb.1.loop.ph: 162 successors: %bb.2(0x80000000) 163 liveins: $r0, $r1, $r2, $r3, $r4, $lr 164 165 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) 166 $lr = t2DoLoopStart renamable $r4 167 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 168 169 bb.2.loop.body: 170 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 171 liveins: $r0, $r1, $r2, $r3, $r12 172 173 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 174 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 175 MVE_VPST 4, implicit $vpr 176 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.addr.a, align 4) 177 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.addr.b, align 4) 178 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 179 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 180 renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, undef renamable $q1 181 renamable $lr = t2LoopDec killed renamable $lr, 1 182 renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg 183 MVE_VPST 8, implicit $vpr 184 renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store 16 into %ir.addr.c, align 4) 185 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 186 tB %bb.3, 14 /* CC::al */, $noreg 187 188 bb.3.exit: 189 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 190 191... 192--- 193name: test_vorn 194alignment: 2 195tracksRegLiveness: true 196registers: [] 197liveins: 198 - { reg: '$r0', virtual-reg: '' } 199 - { reg: '$r1', virtual-reg: '' } 200 - { reg: '$r2', virtual-reg: '' } 201 - { reg: '$r3', virtual-reg: '' } 202frameInfo: 203 stackSize: 8 204 offsetAdjustment: 0 205 maxAlignment: 4 206fixedStack: 207 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 208 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 209 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 210stack: 211 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 212 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 213 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 214 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 215 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 216 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 217callSites: [] 218constants: [] 219machineFunctionInfo: {} 220body: | 221 ; CHECK-LABEL: name: test_vorn 222 ; CHECK: bb.0.entry: 223 ; CHECK: successors: %bb.1(0x80000000) 224 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 225 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 226 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 227 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 228 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 229 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 230 ; CHECK: t2IT 11, 8, implicit-def $itstate 231 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 232 ; CHECK: bb.1.loop.ph: 233 ; CHECK: successors: %bb.2(0x80000000) 234 ; CHECK: liveins: $r0, $r1, $r2, $r3 235 ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) 236 ; CHECK: dead $lr = t2DLS renamable $r4 237 ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 238 ; CHECK: bb.2.loop.body: 239 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 240 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 241 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 242 ; CHECK: MVE_VPST 4, implicit $vpr 243 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.addr.b, align 4) 244 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.addr.a, align 4) 245 ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 246 ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 247 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 248 ; CHECK: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 249 ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg 250 ; CHECK: MVE_VPST 8, implicit $vpr 251 ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store 16 into %ir.addr.c, align 4) 252 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 253 ; CHECK: bb.3.exit: 254 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 255 bb.0.entry: 256 successors: %bb.1(0x80000000) 257 liveins: $r0, $r1, $r2, $r3, $r4, $lr 258 259 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 260 frame-setup CFI_INSTRUCTION def_cfa_offset 8 261 frame-setup CFI_INSTRUCTION offset $lr, -4 262 frame-setup CFI_INSTRUCTION offset $r4, -8 263 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 264 t2IT 11, 8, implicit-def $itstate 265 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 266 267 bb.1.loop.ph: 268 successors: %bb.2(0x80000000) 269 liveins: $r0, $r1, $r2, $r3, $r4, $lr 270 271 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) 272 $lr = t2DoLoopStart renamable $r4 273 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 274 275 bb.2.loop.body: 276 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 277 liveins: $r0, $r1, $r2, $r3, $r12 278 279 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 280 MVE_VPST 4, implicit $vpr 281 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.addr.b, align 4) 282 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.addr.a, align 4) 283 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 284 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 285 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 286 renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 287 renamable $lr = t2LoopDec killed renamable $lr, 1 288 renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg 289 MVE_VPST 8, implicit $vpr 290 renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store 16 into %ir.addr.c, align 4) 291 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 292 tB %bb.3, 14 /* CC::al */, $noreg 293 294 bb.3.exit: 295 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 296 297... 298