1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3--- | 4 define dso_local void @legal_vaddv_s32(i16* nocapture readonly %a, i32* %c, i32 %N) { 5 entry: 6 %cmp9 = icmp eq i32 %N, 0 7 %tmp = add i32 %N, 3 8 %tmp1 = lshr i32 %tmp, 2 9 %tmp2 = shl nuw i32 %tmp1, 2 10 %tmp3 = add i32 %tmp2, -4 11 %tmp4 = lshr i32 %tmp3, 2 12 %tmp5 = add nuw nsw i32 %tmp4, 1 13 br i1 %cmp9, label %exit, label %vector.ph 14 15 vector.ph: ; preds = %entry 16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 17 br label %vector.body 18 19 vector.body: ; preds = %vector.body, %vector.ph 20 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 21 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 22 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 23 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 24 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 25 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 26 %tmp9 = sub i32 %tmp7, 4 27 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 28 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 29 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10) 30 store i32 %tmp11, i32* %store.addr 31 %store.next = getelementptr i32, i32* %store.addr, i32 1 32 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 33 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 34 %tmp13 = icmp ne i32 %tmp12, 0 35 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 36 br i1 %tmp13, label %vector.body, label %exit 37 38 exit: ; preds = %vector.body, %entry 39 ret void 40 } 41 42 define dso_local void @legal_vaddv_s16(i16* nocapture readonly %a, i32* %c, i32 %N) { 43 entry: 44 %cmp9 = icmp eq i32 %N, 0 45 %tmp = add i32 %N, 3 46 %tmp1 = lshr i32 %tmp, 2 47 %tmp2 = shl nuw i32 %tmp1, 2 48 %tmp3 = add i32 %tmp2, -4 49 %tmp4 = lshr i32 %tmp3, 2 50 %tmp5 = add nuw nsw i32 %tmp4, 1 51 br i1 %cmp9, label %exit, label %vector.ph 52 53 vector.ph: ; preds = %entry 54 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 55 br label %vector.body 56 57 vector.body: ; preds = %vector.body, %vector.ph 58 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 59 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 60 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 61 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 62 %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* 63 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 64 %tmp9 = sub i32 %tmp7, 8 65 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 66 %sext = sext <8 x i16> %wide.masked.load to <8 x i32> 67 %tmp11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sext) 68 store i32 %tmp11, i32* %store.addr 69 %store.next = getelementptr i32, i32* %store.addr, i32 1 70 %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 71 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 72 %tmp13 = icmp ne i32 %tmp12, 0 73 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 74 br i1 %tmp13, label %vector.body, label %exit 75 76 exit: ; preds = %vector.body, %entry 77 ret void 78 } 79 80 define dso_local void @legal_vaddv_s8(i8* nocapture readonly %a, i32* %c, i32 %N) { 81 entry: 82 %cmp9 = icmp eq i32 %N, 0 83 %tmp = add i32 %N, 7 84 %tmp1 = lshr i32 %tmp, 3 85 %tmp2 = shl nuw i32 %tmp1, 3 86 %tmp3 = add i32 %tmp2, -7 87 %tmp4 = lshr i32 %tmp3, 3 88 %tmp5 = add nuw nsw i32 %tmp4, 1 89 br i1 %cmp9, label %exit, label %vector.ph 90 91 vector.ph: ; preds = %entry 92 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 93 br label %vector.body 94 95 vector.body: ; preds = %vector.body, %vector.ph 96 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 97 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 98 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 99 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 100 %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* 101 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 102 %tmp9 = sub i32 %tmp7, 16 103 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 104 %sext = sext <16 x i8> %wide.masked.load to <16 x i32> 105 %tmp11 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %sext) 106 store i32 %tmp11, i32* %store.addr 107 %store.next = getelementptr i32, i32* %store.addr, i32 1 108 %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 109 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 110 %tmp13 = icmp ne i32 %tmp12, 0 111 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 112 br i1 %tmp13, label %vector.body, label %exit 113 114 exit: ; preds = %vector.body, %entry 115 ret void 116 } 117 118 define dso_local i32 @legal_vaddva_s32(i16* nocapture readonly %a, i32 %N) { 119 entry: 120 %cmp9 = icmp eq i32 %N, 0 121 %tmp = add i32 %N, 3 122 %tmp1 = lshr i32 %tmp, 2 123 %tmp2 = shl nuw i32 %tmp1, 2 124 %tmp3 = add i32 %tmp2, -4 125 %tmp4 = lshr i32 %tmp3, 2 126 %tmp5 = add nuw nsw i32 %tmp4, 1 127 br i1 %cmp9, label %exit, label %vector.ph 128 129 vector.ph: ; preds = %entry 130 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 131 br label %vector.body 132 133 vector.body: ; preds = %vector.body, %vector.ph 134 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 135 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 136 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 137 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 138 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 139 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 140 %tmp9 = sub i32 %tmp7, 4 141 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 142 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 143 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10) 144 %acc.next = add i32 %tmp11, %acc 145 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 146 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 147 %tmp13 = icmp ne i32 %tmp12, 0 148 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 149 br i1 %tmp13, label %vector.body, label %exit 150 151 exit: ; preds = %vector.body, %entry 152 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 153 ret i32 %res 154 } 155 156 define dso_local void @illegal_vaddv_s32(i16* nocapture readonly %a, i32* %c, i32 %N) { 157 entry: 158 %cmp9 = icmp eq i32 %N, 0 159 %tmp = add i32 %N, 3 160 %tmp1 = lshr i32 %tmp, 2 161 %tmp2 = shl nuw i32 %tmp1, 2 162 %tmp3 = add i32 %tmp2, -4 163 %tmp4 = lshr i32 %tmp3, 2 164 %tmp5 = add nuw nsw i32 %tmp4, 1 165 br i1 %cmp9, label %exit, label %vector.ph 166 167 vector.ph: ; preds = %entry 168 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 169 br label %vector.body 170 171 vector.body: ; preds = %vector.body, %vector.ph 172 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 173 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 174 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 175 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 176 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 177 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 178 %tmp9 = sub i32 %tmp7, 4 179 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 180 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 181 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 182 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 183 store i32 %tmp11, i32* %store.addr 184 %store.next = getelementptr i32, i32* %store.addr, i32 1 185 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 186 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 187 %tmp13 = icmp ne i32 %tmp12, 0 188 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 189 br i1 %tmp13, label %vector.body, label %exit 190 191 exit: ; preds = %vector.body, %entry 192 ret void 193 } 194 195 define dso_local i32 @illegal_vaddva_s32(i16* nocapture readonly %a, i32 %N) { 196 entry: 197 %cmp9 = icmp eq i32 %N, 0 198 %tmp = add i32 %N, 3 199 %tmp1 = lshr i32 %tmp, 2 200 %tmp2 = shl nuw i32 %tmp1, 2 201 %tmp3 = add i32 %tmp2, -4 202 %tmp4 = lshr i32 %tmp3, 2 203 %tmp5 = add nuw nsw i32 %tmp4, 1 204 br i1 %cmp9, label %exit, label %vector.ph 205 206 vector.ph: ; preds = %entry 207 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 208 br label %vector.body 209 210 vector.body: ; preds = %vector.body, %vector.ph 211 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 212 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 213 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 214 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 215 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 216 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 217 %tmp9 = sub i32 %tmp7, 4 218 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 219 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 220 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 221 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 222 %acc.next = add i32 %tmp11, %acc 223 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 224 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 225 %tmp13 = icmp ne i32 %tmp12, 0 226 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 227 br i1 %tmp13, label %vector.body, label %exit 228 229 exit: ; preds = %vector.body, %entry 230 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 231 ret i32 %res 232 } 233 234 define dso_local void @illegal_vaddv_u32(i16* nocapture readonly %a, i32* %c, i32 %N) { 235 entry: 236 %cmp9 = icmp eq i32 %N, 0 237 %tmp = add i32 %N, 3 238 %tmp1 = lshr i32 %tmp, 2 239 %tmp2 = shl nuw i32 %tmp1, 2 240 %tmp3 = add i32 %tmp2, -4 241 %tmp4 = lshr i32 %tmp3, 2 242 %tmp5 = add nuw nsw i32 %tmp4, 1 243 br i1 %cmp9, label %exit, label %vector.ph 244 245 vector.ph: ; preds = %entry 246 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 247 br label %vector.body 248 249 vector.body: ; preds = %vector.body, %vector.ph 250 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 251 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 252 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 253 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 254 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 255 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 256 %tmp9 = sub i32 %tmp7, 4 257 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 258 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> 259 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 260 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 261 store i32 %tmp11, i32* %store.addr 262 %store.next = getelementptr i32, i32* %store.addr, i32 1 263 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 264 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 265 %tmp13 = icmp ne i32 %tmp12, 0 266 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 267 br i1 %tmp13, label %vector.body, label %exit 268 269 exit: ; preds = %vector.body, %entry 270 ret void 271 } 272 273 define dso_local i32 @illegal_vaddva_u32(i16* nocapture readonly %a, i32 %N) { 274 entry: 275 %cmp9 = icmp eq i32 %N, 0 276 %tmp = add i32 %N, 3 277 %tmp1 = lshr i32 %tmp, 2 278 %tmp2 = shl nuw i32 %tmp1, 2 279 %tmp3 = add i32 %tmp2, -4 280 %tmp4 = lshr i32 %tmp3, 2 281 %tmp5 = add nuw nsw i32 %tmp4, 1 282 br i1 %cmp9, label %exit, label %vector.ph 283 284 vector.ph: ; preds = %entry 285 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 286 br label %vector.body 287 288 vector.body: ; preds = %vector.body, %vector.ph 289 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 290 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 291 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 292 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 293 %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* 294 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 295 %tmp9 = sub i32 %tmp7, 4 296 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 297 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> 298 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 299 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 300 %acc.next = add i32 %tmp11, %acc 301 %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 302 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 303 %tmp13 = icmp ne i32 %tmp12, 0 304 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 305 br i1 %tmp13, label %vector.body, label %exit 306 307 exit: ; preds = %vector.body, %entry 308 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 309 ret i32 %res 310 } 311 312 define dso_local void @illegal_vaddv_s16(i8* nocapture readonly %a, i32* %c, i32 %N, <8 x i16> %pass) { 313 entry: 314 %cmp9 = icmp eq i32 %N, 0 315 %tmp = add i32 %N, 3 316 %tmp1 = lshr i32 %tmp, 2 317 %tmp2 = shl nuw i32 %tmp1, 2 318 %tmp3 = add i32 %tmp2, -4 319 %tmp4 = lshr i32 %tmp3, 2 320 %tmp5 = add nuw nsw i32 %tmp4, 1 321 br i1 %cmp9, label %exit, label %vector.ph 322 323 vector.ph: ; preds = %entry 324 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 325 br label %vector.body 326 327 vector.body: ; preds = %vector.body, %vector.ph 328 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 329 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 330 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 331 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 332 %lsr.iv17 = bitcast i8* %lsr.iv to <8 x i8>* 333 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 334 %tmp9 = sub i32 %tmp7, 8 335 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) 336 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> 337 %sub = sub <8 x i16> %sext.wide, %pass 338 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 339 %sext.reduce = sext i16 %reduce to i32 340 store i32 %sext.reduce, i32* %store.addr 341 %store.next = getelementptr i32, i32* %store.addr, i32 1 342 %scevgep = getelementptr i8, i8* %lsr.iv, i32 8 343 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 344 %tmp13 = icmp ne i32 %tmp12, 0 345 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 346 br i1 %tmp13, label %vector.body, label %exit 347 348 exit: ; preds = %vector.body, %entry 349 ret void 350 } 351 352 define dso_local i32 @illegal_vaddva_s16(i8* nocapture readonly %a, i32 %N, <8 x i16> %pass) { 353 entry: 354 %cmp9 = icmp eq i32 %N, 0 355 %tmp = add i32 %N, 3 356 %tmp1 = lshr i32 %tmp, 2 357 %tmp2 = shl nuw i32 %tmp1, 2 358 %tmp3 = add i32 %tmp2, -4 359 %tmp4 = lshr i32 %tmp3, 2 360 %tmp5 = add nuw nsw i32 %tmp4, 1 361 br i1 %cmp9, label %exit, label %vector.ph 362 363 vector.ph: ; preds = %entry 364 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 365 br label %vector.body 366 367 vector.body: ; preds = %vector.body, %vector.ph 368 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 369 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 370 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 371 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 372 %lsr.iv17 = bitcast i8* %lsr.iv to <8 x i8>* 373 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 374 %tmp9 = sub i32 %tmp7, 8 375 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) 376 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> 377 %sub = sub <8 x i16> %sext.wide, %pass 378 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 379 %sext.reduce = sext i16 %reduce to i32 380 %acc.next = add i32 %sext.reduce, %acc 381 %scevgep = getelementptr i8, i8* %lsr.iv, i32 8 382 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 383 %tmp13 = icmp ne i32 %tmp12, 0 384 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 385 br i1 %tmp13, label %vector.body, label %exit 386 387 exit: ; preds = %vector.body, %entry 388 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 389 ret i32 %res 390 } 391 392 define dso_local void @illegal_vaddv_u16(i16* nocapture readonly %a, i32* %c, i32 %N, <8 x i16> %pass) { 393 entry: 394 %cmp9 = icmp eq i32 %N, 0 395 %tmp = add i32 %N, 3 396 %tmp1 = lshr i32 %tmp, 2 397 %tmp2 = shl nuw i32 %tmp1, 2 398 %tmp3 = add i32 %tmp2, -4 399 %tmp4 = lshr i32 %tmp3, 2 400 %tmp5 = add nuw nsw i32 %tmp4, 1 401 br i1 %cmp9, label %exit, label %vector.ph 402 403 vector.ph: ; preds = %entry 404 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 405 br label %vector.body 406 407 vector.body: ; preds = %vector.body, %vector.ph 408 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 409 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 410 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 411 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 412 %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* 413 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 414 %tmp9 = sub i32 %tmp7, 8 415 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 416 %sub = sub <8 x i16> %wide.masked.load, %pass 417 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 418 %zext.reduce = zext i16 %reduce to i32 419 store i32 %zext.reduce, i32* %store.addr 420 %store.next = getelementptr i32, i32* %store.addr, i32 1 421 %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 422 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 423 %tmp13 = icmp ne i32 %tmp12, 0 424 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 425 br i1 %tmp13, label %vector.body, label %exit 426 427 exit: ; preds = %vector.body, %entry 428 ret void 429 } 430 431 define dso_local i32 @illegal_vaddva_u16(i16* nocapture readonly %a, i32 %N, <8 x i16> %pass) { 432 entry: 433 %cmp9 = icmp eq i32 %N, 0 434 %tmp = add i32 %N, 3 435 %tmp1 = lshr i32 %tmp, 2 436 %tmp2 = shl nuw i32 %tmp1, 2 437 %tmp3 = add i32 %tmp2, -4 438 %tmp4 = lshr i32 %tmp3, 2 439 %tmp5 = add nuw nsw i32 %tmp4, 1 440 br i1 %cmp9, label %exit, label %vector.ph 441 442 vector.ph: ; preds = %entry 443 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 444 br label %vector.body 445 446 vector.body: ; preds = %vector.body, %vector.ph 447 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 448 %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 449 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 450 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 451 %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* 452 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 453 %tmp9 = sub i32 %tmp7, 8 454 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 455 %sub = sub <8 x i16> %wide.masked.load, %pass 456 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 457 %zext.reduce = zext i16 %reduce to i32 458 %acc.next = add i32 %zext.reduce, %acc 459 %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 460 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 461 %tmp13 = icmp ne i32 %tmp12, 0 462 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 463 br i1 %tmp13, label %vector.body, label %exit 464 465 exit: ; preds = %vector.body, %entry 466 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 467 ret i32 %res 468 } 469 470 define dso_local void @illegal_vaddv_s8(i8* nocapture readonly %a, i32* %c, i32 %N, <16 x i8> %pass) { 471 entry: 472 %cmp9 = icmp eq i32 %N, 0 473 %tmp = add i32 %N, 7 474 %tmp1 = lshr i32 %tmp, 3 475 %tmp2 = shl nuw i32 %tmp1, 3 476 %tmp3 = add i32 %tmp2, -7 477 %tmp4 = lshr i32 %tmp3, 3 478 %tmp5 = add nuw nsw i32 %tmp4, 1 479 br i1 %cmp9, label %exit, label %vector.ph 480 481 vector.ph: ; preds = %entry 482 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 483 br label %vector.body 484 485 vector.body: ; preds = %vector.body, %vector.ph 486 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 487 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 488 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 489 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 490 %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* 491 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 492 %tmp9 = sub i32 %tmp7, 16 493 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 494 %xor = xor <16 x i8> %wide.masked.load, %pass 495 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 496 %sext.reduce = sext i8 %reduce to i32 497 store i32 %sext.reduce, i32* %store.addr 498 %store.next = getelementptr i32, i32* %store.addr, i32 1 499 %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 500 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 501 %tmp13 = icmp ne i32 %tmp12, 0 502 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 503 br i1 %tmp13, label %vector.body, label %exit 504 505 exit: ; preds = %vector.body, %entry 506 ret void 507 } 508 509 define dso_local i32 @illegal_vaddva_s8(i8* nocapture readonly %a, i32 %N, <16 x i8> %pass) { 510 entry: 511 %cmp9 = icmp eq i32 %N, 0 512 %tmp = add i32 %N, 7 513 %tmp1 = lshr i32 %tmp, 3 514 %tmp2 = shl nuw i32 %tmp1, 3 515 %tmp3 = add i32 %tmp2, -7 516 %tmp4 = lshr i32 %tmp3, 3 517 %tmp5 = add nuw nsw i32 %tmp4, 1 518 br i1 %cmp9, label %exit, label %vector.ph 519 520 vector.ph: ; preds = %entry 521 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 522 br label %vector.body 523 524 vector.body: ; preds = %vector.body, %vector.ph 525 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 526 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 527 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 528 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 529 %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* 530 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 531 %tmp9 = sub i32 %tmp7, 16 532 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 533 %xor = xor <16 x i8> %wide.masked.load, %pass 534 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 535 %sext.reduce = sext i8 %reduce to i32 536 %acc.next = add i32 %sext.reduce, %acc 537 %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 538 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 539 %tmp13 = icmp ne i32 %tmp12, 0 540 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 541 br i1 %tmp13, label %vector.body, label %exit 542 543 exit: ; preds = %vector.body, %entry 544 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 545 ret i32 %res 546 } 547 548 define dso_local void @illegal_vaddv_u8(i8* nocapture readonly %a, i32* %c, i32 %N, <16 x i8> %pass) { 549 entry: 550 %cmp9 = icmp eq i32 %N, 0 551 %tmp = add i32 %N, 7 552 %tmp1 = lshr i32 %tmp, 3 553 %tmp2 = shl nuw i32 %tmp1, 3 554 %tmp3 = add i32 %tmp2, -7 555 %tmp4 = lshr i32 %tmp3, 3 556 %tmp5 = add nuw nsw i32 %tmp4, 1 557 br i1 %cmp9, label %exit, label %vector.ph 558 559 vector.ph: ; preds = %entry 560 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 561 br label %vector.body 562 563 vector.body: ; preds = %vector.body, %vector.ph 564 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 565 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 566 %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] 567 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 568 %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* 569 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 570 %tmp9 = sub i32 %tmp7, 16 571 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 572 %xor = xor <16 x i8> %wide.masked.load, %pass 573 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 574 %zext.reduce = zext i8 %reduce to i32 575 store i32 %zext.reduce, i32* %store.addr 576 %store.next = getelementptr i32, i32* %store.addr, i32 1 577 %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 578 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 579 %tmp13 = icmp ne i32 %tmp12, 0 580 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 581 br i1 %tmp13, label %vector.body, label %exit 582 583 exit: ; preds = %vector.body, %entry 584 ret void 585 } 586 587 define dso_local i32 @illegal_vaddva_u8(i8* nocapture readonly %a, i32 %N, <16 x i8> %pass) { 588 entry: 589 %cmp9 = icmp eq i32 %N, 0 590 %tmp = add i32 %N, 7 591 %tmp1 = lshr i32 %tmp, 3 592 %tmp2 = shl nuw i32 %tmp1, 3 593 %tmp3 = add i32 %tmp2, -7 594 %tmp4 = lshr i32 %tmp3, 3 595 %tmp5 = add nuw nsw i32 %tmp4, 1 596 br i1 %cmp9, label %exit, label %vector.ph 597 598 vector.ph: ; preds = %entry 599 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 600 br label %vector.body 601 602 vector.body: ; preds = %vector.body, %vector.ph 603 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 604 %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 605 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 606 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 607 %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* 608 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 609 %tmp9 = sub i32 %tmp7, 16 610 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 611 %xor = xor <16 x i8> %wide.masked.load, %pass 612 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 613 %zext.reduce = zext i8 %reduce to i32 614 %acc.next = add i32 %zext.reduce, %acc 615 %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 616 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 617 %tmp13 = icmp ne i32 %tmp12, 0 618 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 619 br i1 %tmp13, label %vector.body, label %exit 620 621 exit: ; preds = %vector.body, %entry 622 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 623 ret i32 %res 624 } 625 626 define hidden i32 @regalloc_legality_vaddva_u32(i16* %x, i16* %y, i32 %n) { 627 entry: 628 %cmp22 = icmp sgt i32 %n, 0 629 %0 = add i32 %n, 3 630 %1 = icmp slt i32 %n, 4 631 %smin = select i1 %1, i32 %n, i32 4 632 %2 = sub i32 %0, %smin 633 %3 = lshr i32 %2, 2 634 %4 = add nuw nsw i32 %3, 1 635 br i1 %cmp22, label %while.body.preheader, label %while.end 636 637 while.body.preheader: ; preds = %entry 638 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 639 br label %while.body 640 641 while.body: ; preds = %while.body.preheader, %while.body 642 %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 643 %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 644 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 645 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 646 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 647 %tmp3 = bitcast i16* %y.addr.025 to <4 x i16>* 648 %tmp1 = bitcast i16* %x.addr.026 to <4 x i16>* 649 %tmp = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.023) 650 %tmp2 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp1, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) 651 %zext.wide.1 = zext <4 x i16> %tmp2 to <4 x i32> 652 %tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) 653 %zext.wide.2 = zext <4 x i16> %tmp4 to <4 x i32> 654 %or = or <4 x i32> %zext.wide.1, %zext.wide.2 655 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %or) 656 %acc.next = add i32 %reduce, %acc 657 %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 4 658 %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 4 659 %sub = add nsw i32 %n.addr.023, -4 660 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 661 %7 = icmp ne i32 %6, 0 662 br i1 %7, label %while.body, label %while.end 663 664 while.end: ; preds = %while.body, %entry 665 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 666 ret i32 %res 667 } 668 669 define hidden i32 @regalloc_legality_vaddv_u16(i16* %x, i16* %y, i32 %n) { 670 entry: 671 %cmp22 = icmp sgt i32 %n, 0 672 %0 = add i32 %n, 7 673 %1 = icmp slt i32 %n, 8 674 %smin = select i1 %1, i32 %n, i32 8 675 %2 = sub i32 %0, %smin 676 %3 = lshr i32 %2, 3 677 %4 = add nuw nsw i32 %3, 1 678 br i1 %cmp22, label %while.body.preheader, label %while.end 679 680 while.body.preheader: ; preds = %entry 681 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 682 br label %while.body 683 684 while.body: ; preds = %while.body.preheader, %while.body 685 %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 686 %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 687 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 688 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 689 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 690 %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* 691 %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* 692 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 693 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 694 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 695 %or = or <8 x i16> %tmp2, %tmp4 696 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %or) 697 %zext.reduce = zext i16 %reduce to i32 698 %acc.next = add i32 %zext.reduce, %acc 699 %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 700 %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 701 %sub = add nsw i32 %n.addr.023, -8 702 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 703 %7 = icmp ne i32 %6, 0 704 br i1 %7, label %while.body, label %while.end 705 706 while.end: ; preds = %while.body, %entry 707 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 708 ret i32 %res 709 } 710 711 define hidden i32 @regalloc_illegality_vaddva_s32(i16* %x, i16* %y, i16* %z, i32 %n) { 712 entry: 713 %cmp22 = icmp sgt i32 %n, 0 714 %0 = add i32 %n, 7 715 %1 = icmp slt i32 %n, 8 716 %smin = select i1 %1, i32 %n, i32 8 717 %2 = sub i32 %0, %smin 718 %3 = lshr i32 %2, 3 719 %4 = add nuw nsw i32 %3, 1 720 br i1 %cmp22, label %while.body.preheader, label %while.end 721 722 while.body.preheader: ; preds = %entry 723 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 724 br label %while.body 725 726 while.body: ; preds = %while.body.preheader, %while.body 727 %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 728 %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 729 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 730 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 731 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 732 %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* 733 %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* 734 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 735 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 736 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 737 %tmp5 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) 738 %tmp6 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 0) 739 %mul = add <4 x i32> %tmp5, %tmp6 740 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul) 741 %acc.next = add i32 %reduce, %acc 742 %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 743 %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 744 %sub = add nsw i32 %n.addr.023, -8 745 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 746 %7 = icmp ne i32 %6, 0 747 br i1 %7, label %while.body, label %while.end 748 749 while.end: ; preds = %while.body, %entry 750 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 751 ret i32 %res 752 } 753 754 define hidden i32 @illegal_vmull_non_zero(i16* %x, i16* %y, i16* %z, i32 %n) { 755 entry: 756 %cmp22 = icmp sgt i32 %n, 0 757 %0 = add i32 %n, 7 758 %1 = icmp slt i32 %n, 8 759 %smin = select i1 %1, i32 %n, i32 8 760 %2 = sub i32 %0, %smin 761 %3 = lshr i32 %2, 3 762 %4 = add nuw nsw i32 %3, 1 763 br i1 %cmp22, label %while.body.preheader, label %while.end 764 765 while.body.preheader: ; preds = %entry 766 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 767 br label %while.body 768 769 while.body: ; preds = %while.body.preheader, %while.body 770 %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 771 %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 772 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 773 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 774 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 775 %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* 776 %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* 777 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 778 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 779 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 780 %mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) 781 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul) 782 %acc.next = add i32 %reduce, %acc 783 %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 784 %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 785 %sub = add nsw i32 %n.addr.023, -8 786 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 787 %7 = icmp ne i32 %6, 0 788 br i1 %7, label %while.body, label %while.end 789 790 while.end: ; preds = %while.body, %entry 791 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 792 ret i32 %res 793 } 794 795 declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>) 796 declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) 797 declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>) 798 declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) 799 declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>) 800 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 801 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) 802 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) 803 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) 804 declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) 805 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) 806 declare i32 @llvm.start.loop.iterations.i32(i32) 807 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 808 declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) 809 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 810 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 811 declare <16 x i1> @llvm.arm.mve.vctp8(i32) 812 813... 814--- 815name: legal_vaddv_s32 816alignment: 2 817tracksRegLiveness: true 818registers: [] 819liveins: 820 - { reg: '$r0', virtual-reg: '' } 821 - { reg: '$r1', virtual-reg: '' } 822 - { reg: '$r2', virtual-reg: '' } 823frameInfo: 824 stackSize: 8 825 offsetAdjustment: 0 826 maxAlignment: 4 827 stackProtector: '' 828 maxCallFrameSize: 0 829 cvBytesOfCalleeSavedRegisters: 0 830 localFrameSize: 0 831 savePoint: '' 832 restorePoint: '' 833fixedStack: [] 834stack: 835 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 836 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 837 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 838 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 839 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 840 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 841callSites: [] 842constants: [] 843machineFunctionInfo: {} 844body: | 845 ; CHECK-LABEL: name: legal_vaddv_s32 846 ; CHECK: bb.0.entry: 847 ; CHECK: successors: %bb.1(0x80000000) 848 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 849 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 850 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 851 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 852 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 853 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 854 ; CHECK: t2IT 0, 8, implicit-def $itstate 855 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 856 ; CHECK: bb.1.vector.ph: 857 ; CHECK: successors: %bb.2(0x80000000) 858 ; CHECK: liveins: $r0, $r1, $r2 859 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 860 ; CHECK: bb.2.vector.body: 861 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 862 ; CHECK: liveins: $lr, $r0, $r1 863 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2) 864 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 865 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 866 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 867 ; CHECK: bb.3.exit: 868 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 869 bb.0.entry: 870 successors: %bb.1(0x80000000) 871 liveins: $r0, $r1, $r2, $r7, $lr 872 873 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 874 frame-setup CFI_INSTRUCTION def_cfa_offset 8 875 frame-setup CFI_INSTRUCTION offset $lr, -4 876 frame-setup CFI_INSTRUCTION offset $r7, -8 877 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 878 t2IT 0, 8, implicit-def $itstate 879 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 880 881 bb.1.vector.ph: 882 successors: %bb.2(0x80000000) 883 liveins: $r0, $r1, $r2, $r7, $lr 884 885 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 886 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 887 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 888 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 889 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 890 $lr = t2DoLoopStart renamable $r12 891 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 892 893 bb.2.vector.body: 894 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 895 liveins: $r0, $r1, $r2, $r3 896 897 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 898 MVE_VPST 8, implicit $vpr 899 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 900 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 901 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 902 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 903 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 904 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 905 renamable $lr = t2LoopDec killed renamable $lr, 1 906 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 907 tB %bb.3, 14 /* CC::al */, $noreg 908 909 bb.3.exit: 910 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 911 912... 913--- 914name: legal_vaddv_s16 915alignment: 2 916tracksRegLiveness: true 917registers: [] 918liveins: 919 - { reg: '$r0', virtual-reg: '' } 920 - { reg: '$r1', virtual-reg: '' } 921 - { reg: '$r2', virtual-reg: '' } 922frameInfo: 923 stackSize: 8 924 offsetAdjustment: 0 925 maxAlignment: 4 926 stackProtector: '' 927 maxCallFrameSize: 0 928 cvBytesOfCalleeSavedRegisters: 0 929 localFrameSize: 0 930 savePoint: '' 931 restorePoint: '' 932fixedStack: [] 933stack: 934 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 935 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 936 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 937 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 938 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 939 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 940callSites: [] 941constants: [] 942machineFunctionInfo: {} 943body: | 944 ; CHECK-LABEL: name: legal_vaddv_s16 945 ; CHECK: bb.0.entry: 946 ; CHECK: successors: %bb.1(0x80000000) 947 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 948 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 949 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 950 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 951 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 952 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 953 ; CHECK: t2IT 0, 8, implicit-def $itstate 954 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 955 ; CHECK: bb.1.vector.ph: 956 ; CHECK: successors: %bb.2(0x80000000) 957 ; CHECK: liveins: $r0, $r1, $r2 958 ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 959 ; CHECK: bb.2.vector.body: 960 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 961 ; CHECK: liveins: $lr, $r0, $r1 962 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 2) 963 ; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg 964 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 965 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 966 ; CHECK: bb.3.exit: 967 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 968 bb.0.entry: 969 successors: %bb.1(0x80000000) 970 liveins: $r0, $r1, $r2, $r7, $lr 971 972 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 973 frame-setup CFI_INSTRUCTION def_cfa_offset 8 974 frame-setup CFI_INSTRUCTION offset $lr, -4 975 frame-setup CFI_INSTRUCTION offset $r7, -8 976 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 977 t2IT 0, 8, implicit-def $itstate 978 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 979 980 bb.1.vector.ph: 981 successors: %bb.2(0x80000000) 982 liveins: $r0, $r1, $r2, $r7, $lr 983 984 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 985 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 986 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 987 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 988 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 989 $lr = t2DoLoopStart renamable $r12 990 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 991 992 bb.2.vector.body: 993 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 994 liveins: $r0, $r1, $r2, $r3 995 996 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 997 MVE_VPST 8, implicit $vpr 998 renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) 999 renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg 1000 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1001 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1002 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1003 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1004 renamable $lr = t2LoopDec killed renamable $lr, 1 1005 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1006 tB %bb.3, 14 /* CC::al */, $noreg 1007 1008 bb.3.exit: 1009 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1010 1011... 1012--- 1013name: legal_vaddv_s8 1014alignment: 2 1015tracksRegLiveness: true 1016registers: [] 1017liveins: 1018 - { reg: '$r0', virtual-reg: '' } 1019 - { reg: '$r1', virtual-reg: '' } 1020 - { reg: '$r2', virtual-reg: '' } 1021frameInfo: 1022 stackSize: 8 1023 offsetAdjustment: 0 1024 maxAlignment: 4 1025 stackProtector: '' 1026 maxCallFrameSize: 0 1027 cvBytesOfCalleeSavedRegisters: 0 1028 localFrameSize: 0 1029 savePoint: '' 1030 restorePoint: '' 1031fixedStack: [] 1032stack: 1033 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1034 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1035 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1036 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1037 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1038 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1039callSites: [] 1040constants: [] 1041machineFunctionInfo: {} 1042body: | 1043 ; CHECK-LABEL: name: legal_vaddv_s8 1044 ; CHECK: bb.0.entry: 1045 ; CHECK: successors: %bb.1(0x80000000) 1046 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1047 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1048 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1049 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1050 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1051 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1052 ; CHECK: t2IT 0, 8, implicit-def $itstate 1053 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1054 ; CHECK: bb.1.vector.ph: 1055 ; CHECK: successors: %bb.2(0x80000000) 1056 ; CHECK: liveins: $r0, $r1, $r2 1057 ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2 1058 ; CHECK: bb.2.vector.body: 1059 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1060 ; CHECK: liveins: $lr, $r0, $r1 1061 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 1) 1062 ; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg 1063 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1064 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 1065 ; CHECK: bb.3.exit: 1066 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1067 bb.0.entry: 1068 successors: %bb.1(0x80000000) 1069 liveins: $r0, $r1, $r2, $r7, $lr 1070 1071 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1072 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1073 frame-setup CFI_INSTRUCTION offset $lr, -4 1074 frame-setup CFI_INSTRUCTION offset $r7, -8 1075 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1076 t2IT 0, 8, implicit-def $itstate 1077 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1078 1079 bb.1.vector.ph: 1080 successors: %bb.2(0x80000000) 1081 liveins: $r0, $r1, $r2, $r7, $lr 1082 1083 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 1084 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 1085 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 1086 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1087 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 1088 $lr = t2DoLoopStart renamable $r12 1089 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1090 1091 bb.2.vector.body: 1092 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1093 liveins: $r0, $r1, $r2, $r3 1094 1095 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg 1096 MVE_VPST 8, implicit $vpr 1097 renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 1098 renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg 1099 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1100 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1101 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1102 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1103 renamable $lr = t2LoopDec killed renamable $lr, 1 1104 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1105 tB %bb.3, 14 /* CC::al */, $noreg 1106 1107 bb.3.exit: 1108 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1109 1110... 1111--- 1112name: legal_vaddva_s32 1113alignment: 2 1114tracksRegLiveness: true 1115registers: [] 1116liveins: 1117 - { reg: '$r0', virtual-reg: '' } 1118 - { reg: '$r1', virtual-reg: '' } 1119frameInfo: 1120 stackSize: 8 1121 offsetAdjustment: 0 1122 maxAlignment: 4 1123 stackProtector: '' 1124 maxCallFrameSize: 0 1125 cvBytesOfCalleeSavedRegisters: 0 1126 localFrameSize: 0 1127 savePoint: '' 1128 restorePoint: '' 1129fixedStack: [] 1130stack: 1131 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1132 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1133 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1134 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1135 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1136 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1137callSites: [] 1138constants: [] 1139machineFunctionInfo: {} 1140body: | 1141 ; CHECK-LABEL: name: legal_vaddva_s32 1142 ; CHECK: bb.0.entry: 1143 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1144 ; CHECK: liveins: $lr, $r0, $r1, $r7 1145 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1146 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1147 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1148 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1149 ; CHECK: tCBZ $r1, %bb.4 1150 ; CHECK: bb.1.vector.ph: 1151 ; CHECK: successors: %bb.2(0x80000000) 1152 ; CHECK: liveins: $r0, $r1 1153 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 1154 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1155 ; CHECK: bb.2.vector.body: 1156 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1157 ; CHECK: liveins: $lr, $r0, $r2 1158 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2) 1159 ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1160 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 1161 ; CHECK: bb.3.exit: 1162 ; CHECK: liveins: $r2 1163 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1164 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1165 ; CHECK: bb.4: 1166 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1167 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1168 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1169 bb.0.entry: 1170 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1171 liveins: $r0, $r1, $r7, $lr 1172 1173 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1174 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1175 frame-setup CFI_INSTRUCTION offset $lr, -4 1176 frame-setup CFI_INSTRUCTION offset $r7, -8 1177 tCBZ $r1, %bb.4 1178 1179 bb.1.vector.ph: 1180 successors: %bb.2(0x80000000) 1181 liveins: $r0, $r1 1182 1183 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1184 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1185 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1186 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1187 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1188 $lr = t2DoLoopStart renamable $r2 1189 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1190 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1191 1192 bb.2.vector.body: 1193 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1194 liveins: $r0, $r1, $r2, $r3 1195 1196 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 1197 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1198 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1199 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1200 MVE_VPST 8, implicit $vpr 1201 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1202 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1203 renamable $lr = t2LoopDec killed renamable $lr, 1 1204 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1205 tB %bb.3, 14 /* CC::al */, $noreg 1206 1207 bb.3.exit: 1208 liveins: $r2 1209 1210 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1211 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1212 1213 bb.4: 1214 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1215 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1216 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1217 1218... 1219--- 1220name: illegal_vaddv_s32 1221alignment: 2 1222tracksRegLiveness: true 1223registers: [] 1224liveins: 1225 - { reg: '$r0', virtual-reg: '' } 1226 - { reg: '$r1', virtual-reg: '' } 1227 - { reg: '$r2', virtual-reg: '' } 1228frameInfo: 1229 stackSize: 8 1230 offsetAdjustment: 0 1231 maxAlignment: 4 1232 stackProtector: '' 1233 maxCallFrameSize: 0 1234 cvBytesOfCalleeSavedRegisters: 0 1235 localFrameSize: 0 1236 savePoint: '' 1237 restorePoint: '' 1238fixedStack: [] 1239stack: 1240 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1241 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1242 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1243 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1244 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1245 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1246callSites: [] 1247constants: [] 1248machineFunctionInfo: {} 1249body: | 1250 ; CHECK-LABEL: name: illegal_vaddv_s32 1251 ; CHECK: bb.0.entry: 1252 ; CHECK: successors: %bb.1(0x80000000) 1253 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1254 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1255 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1256 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1257 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1258 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1259 ; CHECK: t2IT 0, 8, implicit-def $itstate 1260 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1261 ; CHECK: bb.1.vector.ph: 1262 ; CHECK: successors: %bb.2(0x80000000) 1263 ; CHECK: liveins: $r0, $r1, $r2 1264 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1265 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1266 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1267 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1268 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1269 ; CHECK: dead $lr = t2DLS renamable $r12 1270 ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1271 ; CHECK: bb.2.vector.body: 1272 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1273 ; CHECK: liveins: $r0, $r1, $r2, $r3 1274 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 1275 ; CHECK: MVE_VPST 8, implicit $vpr 1276 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1277 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1278 ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1279 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 1280 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1281 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1282 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1283 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1284 ; CHECK: bb.3.exit: 1285 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1286 bb.0.entry: 1287 successors: %bb.1(0x80000000) 1288 liveins: $r0, $r1, $r2, $r7, $lr 1289 1290 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1291 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1292 frame-setup CFI_INSTRUCTION offset $lr, -4 1293 frame-setup CFI_INSTRUCTION offset $r7, -8 1294 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1295 t2IT 0, 8, implicit-def $itstate 1296 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1297 1298 bb.1.vector.ph: 1299 successors: %bb.2(0x80000000) 1300 liveins: $r0, $r1, $r2, $r7, $lr 1301 1302 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1303 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1304 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1305 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1306 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1307 $lr = t2DoLoopStart renamable $r12 1308 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1309 1310 bb.2.vector.body: 1311 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1312 liveins: $r0, $r1, $r2, $r3 1313 1314 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 1315 MVE_VPST 8, implicit $vpr 1316 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1317 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1318 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1319 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 1320 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1321 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1322 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1323 renamable $lr = t2LoopDec killed renamable $lr, 1 1324 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1325 tB %bb.3, 14 /* CC::al */, $noreg 1326 1327 bb.3.exit: 1328 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1329 1330... 1331--- 1332name: illegal_vaddva_s32 1333alignment: 2 1334tracksRegLiveness: true 1335registers: [] 1336liveins: 1337 - { reg: '$r0', virtual-reg: '' } 1338 - { reg: '$r1', virtual-reg: '' } 1339frameInfo: 1340 stackSize: 8 1341 offsetAdjustment: 0 1342 maxAlignment: 4 1343 stackProtector: '' 1344 maxCallFrameSize: 0 1345 cvBytesOfCalleeSavedRegisters: 0 1346 localFrameSize: 0 1347 savePoint: '' 1348 restorePoint: '' 1349fixedStack: [] 1350stack: 1351 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1352 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1353 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1354 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1355 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1356 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1357callSites: [] 1358constants: [] 1359machineFunctionInfo: {} 1360body: | 1361 ; CHECK-LABEL: name: illegal_vaddva_s32 1362 ; CHECK: bb.0.entry: 1363 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1364 ; CHECK: liveins: $lr, $r0, $r1, $r7 1365 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1366 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1367 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1368 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1369 ; CHECK: tCBZ $r1, %bb.4 1370 ; CHECK: bb.1.vector.ph: 1371 ; CHECK: successors: %bb.2(0x80000000) 1372 ; CHECK: liveins: $r0, $r1 1373 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1374 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1375 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1376 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1377 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1378 ; CHECK: dead $lr = t2DLS renamable $r2 1379 ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1380 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1381 ; CHECK: bb.2.vector.body: 1382 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1383 ; CHECK: liveins: $r0, $r1, $r2, $r3 1384 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 1385 ; CHECK: MVE_VPST 8, implicit $vpr 1386 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1387 ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1388 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1389 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1390 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1391 ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1392 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1393 ; CHECK: bb.3.exit: 1394 ; CHECK: liveins: $r2 1395 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1396 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1397 ; CHECK: bb.4: 1398 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1399 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1400 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1401 bb.0.entry: 1402 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1403 liveins: $r0, $r1, $r7, $lr 1404 1405 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1406 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1407 frame-setup CFI_INSTRUCTION offset $lr, -4 1408 frame-setup CFI_INSTRUCTION offset $r7, -8 1409 tCBZ $r1, %bb.4 1410 1411 bb.1.vector.ph: 1412 successors: %bb.2(0x80000000) 1413 liveins: $r0, $r1 1414 1415 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1416 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1417 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1418 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1419 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1420 $lr = t2DoLoopStart renamable $r2 1421 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1422 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1423 1424 bb.2.vector.body: 1425 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1426 liveins: $r0, $r1, $r2, $r3 1427 1428 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 1429 MVE_VPST 8, implicit $vpr 1430 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1431 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1432 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1433 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1434 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1435 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1436 renamable $lr = t2LoopDec killed renamable $lr, 1 1437 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1438 tB %bb.3, 14 /* CC::al */, $noreg 1439 1440 bb.3.exit: 1441 liveins: $r2 1442 1443 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1444 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1445 1446 bb.4: 1447 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1448 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1449 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1450 1451... 1452--- 1453name: illegal_vaddv_u32 1454alignment: 2 1455tracksRegLiveness: true 1456registers: [] 1457liveins: 1458 - { reg: '$r0', virtual-reg: '' } 1459 - { reg: '$r1', virtual-reg: '' } 1460 - { reg: '$r2', virtual-reg: '' } 1461frameInfo: 1462 stackSize: 8 1463 offsetAdjustment: 0 1464 maxAlignment: 4 1465 stackProtector: '' 1466 maxCallFrameSize: 0 1467 cvBytesOfCalleeSavedRegisters: 0 1468 localFrameSize: 0 1469 savePoint: '' 1470 restorePoint: '' 1471fixedStack: [] 1472stack: 1473 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1474 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1475 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1476 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1477 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1478 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1479callSites: [] 1480constants: [] 1481machineFunctionInfo: {} 1482body: | 1483 ; CHECK-LABEL: name: illegal_vaddv_u32 1484 ; CHECK: bb.0.entry: 1485 ; CHECK: successors: %bb.1(0x80000000) 1486 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1487 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1488 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1489 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1490 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1491 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1492 ; CHECK: t2IT 0, 8, implicit-def $itstate 1493 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1494 ; CHECK: bb.1.vector.ph: 1495 ; CHECK: successors: %bb.2(0x80000000) 1496 ; CHECK: liveins: $r0, $r1, $r2 1497 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1498 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1499 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1500 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1501 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1502 ; CHECK: dead $lr = t2DLS renamable $r12 1503 ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1504 ; CHECK: bb.2.vector.body: 1505 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1506 ; CHECK: liveins: $r0, $r1, $r2, $r3 1507 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 1508 ; CHECK: MVE_VPST 8, implicit $vpr 1509 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1510 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1511 ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1512 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 1513 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1514 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1515 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1516 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1517 ; CHECK: bb.3.exit: 1518 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1519 bb.0.entry: 1520 successors: %bb.1(0x80000000) 1521 liveins: $r0, $r1, $r2, $r7, $lr 1522 1523 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1524 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1525 frame-setup CFI_INSTRUCTION offset $lr, -4 1526 frame-setup CFI_INSTRUCTION offset $r7, -8 1527 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1528 t2IT 0, 8, implicit-def $itstate 1529 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1530 1531 bb.1.vector.ph: 1532 successors: %bb.2(0x80000000) 1533 liveins: $r0, $r1, $r2, $r7, $lr 1534 1535 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1536 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1537 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1538 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1539 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1540 $lr = t2DoLoopStart renamable $r12 1541 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1542 1543 bb.2.vector.body: 1544 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1545 liveins: $r0, $r1, $r2, $r3 1546 1547 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 1548 MVE_VPST 8, implicit $vpr 1549 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1550 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1551 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1552 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg 1553 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1554 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1555 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1556 renamable $lr = t2LoopDec killed renamable $lr, 1 1557 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1558 tB %bb.3, 14 /* CC::al */, $noreg 1559 1560 bb.3.exit: 1561 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1562 1563... 1564--- 1565name: illegal_vaddva_u32 1566alignment: 2 1567tracksRegLiveness: true 1568registers: [] 1569liveins: 1570 - { reg: '$r0', virtual-reg: '' } 1571 - { reg: '$r1', virtual-reg: '' } 1572frameInfo: 1573 stackSize: 8 1574 offsetAdjustment: 0 1575 maxAlignment: 4 1576 stackProtector: '' 1577 maxCallFrameSize: 0 1578 cvBytesOfCalleeSavedRegisters: 0 1579 localFrameSize: 0 1580 savePoint: '' 1581 restorePoint: '' 1582fixedStack: [] 1583stack: 1584 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1585 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1586 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1587 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1588 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1589 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1590callSites: [] 1591constants: [] 1592machineFunctionInfo: {} 1593body: | 1594 ; CHECK-LABEL: name: illegal_vaddva_u32 1595 ; CHECK: bb.0.entry: 1596 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1597 ; CHECK: liveins: $lr, $r0, $r1, $r7 1598 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1599 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1600 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1601 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1602 ; CHECK: tCBZ $r1, %bb.4 1603 ; CHECK: bb.1.vector.ph: 1604 ; CHECK: successors: %bb.2(0x80000000) 1605 ; CHECK: liveins: $r0, $r1 1606 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1607 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1608 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1609 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1610 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1611 ; CHECK: dead $lr = t2DLS renamable $r2 1612 ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1613 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1614 ; CHECK: bb.2.vector.body: 1615 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1616 ; CHECK: liveins: $r0, $r1, $r2, $r3 1617 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 1618 ; CHECK: MVE_VPST 8, implicit $vpr 1619 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1620 ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1621 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1622 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1623 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1624 ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1625 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1626 ; CHECK: bb.3.exit: 1627 ; CHECK: liveins: $r2 1628 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1629 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1630 ; CHECK: bb.4: 1631 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1632 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1633 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1634 bb.0.entry: 1635 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1636 liveins: $r0, $r1, $r7, $lr 1637 1638 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1639 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1640 frame-setup CFI_INSTRUCTION offset $lr, -4 1641 frame-setup CFI_INSTRUCTION offset $r7, -8 1642 tCBZ $r1, %bb.4 1643 1644 bb.1.vector.ph: 1645 successors: %bb.2(0x80000000) 1646 liveins: $r0, $r1 1647 1648 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1649 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1650 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1651 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1652 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1653 $lr = t2DoLoopStart renamable $r2 1654 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1655 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1656 1657 bb.2.vector.body: 1658 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1659 liveins: $r0, $r1, $r2, $r3 1660 1661 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 1662 MVE_VPST 8, implicit $vpr 1663 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) 1664 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1665 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 1666 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1667 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1668 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 1669 renamable $lr = t2LoopDec killed renamable $lr, 1 1670 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1671 tB %bb.3, 14 /* CC::al */, $noreg 1672 1673 bb.3.exit: 1674 liveins: $r2 1675 1676 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1677 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1678 1679 bb.4: 1680 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1681 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1682 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1683 1684... 1685--- 1686name: illegal_vaddv_s16 1687alignment: 2 1688tracksRegLiveness: true 1689registers: [] 1690liveins: 1691 - { reg: '$r0', virtual-reg: '' } 1692 - { reg: '$r1', virtual-reg: '' } 1693 - { reg: '$r2', virtual-reg: '' } 1694frameInfo: 1695 stackSize: 8 1696 offsetAdjustment: 0 1697 maxAlignment: 8 1698 stackProtector: '' 1699 maxCallFrameSize: 0 1700 cvBytesOfCalleeSavedRegisters: 0 1701 localFrameSize: 0 1702 savePoint: '' 1703 restorePoint: '' 1704fixedStack: 1705 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 1706 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 1707 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1708stack: 1709 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1710 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1711 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1712 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1713 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 1714 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1715callSites: [] 1716constants: [] 1717machineFunctionInfo: {} 1718body: | 1719 ; CHECK-LABEL: name: illegal_vaddv_s16 1720 ; CHECK: bb.0.entry: 1721 ; CHECK: successors: %bb.1(0x80000000) 1722 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 1723 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1724 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1725 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1726 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 1727 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1728 ; CHECK: t2IT 0, 8, implicit-def $itstate 1729 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 1730 ; CHECK: bb.1.vector.ph: 1731 ; CHECK: successors: %bb.2(0x80000000) 1732 ; CHECK: liveins: $r0, $r1, $r2 1733 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1734 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1735 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1736 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1737 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1738 ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 1739 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 1740 ; CHECK: dead $lr = t2DLS renamable $r12 1741 ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1742 ; CHECK: bb.2.vector.body: 1743 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1744 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 1745 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 1746 ; CHECK: MVE_VPST 8, implicit $vpr 1747 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) 1748 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 1749 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1750 ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 1751 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1752 ; CHECK: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 1753 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1754 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1755 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1756 ; CHECK: bb.3.exit: 1757 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 1758 1759 bb.0.entry: 1760 successors: %bb.1(0x80000000) 1761 liveins: $r0, $r1, $r2, $r4, $lr 1762 1763 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1764 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1765 frame-setup CFI_INSTRUCTION offset $lr, -4 1766 frame-setup CFI_INSTRUCTION offset $r4, -8 1767 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1768 t2IT 0, 8, implicit-def $itstate 1769 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 1770 1771 bb.1.vector.ph: 1772 successors: %bb.2(0x80000000) 1773 liveins: $r0, $r1, $r2, $r4, $lr 1774 1775 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1776 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1777 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1778 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1779 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1780 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 1781 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 1782 $lr = t2DoLoopStart renamable $r12 1783 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1784 1785 bb.2.vector.body: 1786 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1787 liveins: $q0, $r0, $r1, $r2, $r4 1788 1789 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 1790 MVE_VPST 8, implicit $vpr 1791 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) 1792 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 1793 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1794 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 1795 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1796 renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 1797 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1798 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 1799 renamable $lr = t2LoopDec killed renamable $lr, 1 1800 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1801 tB %bb.3, 14 /* CC::al */, $noreg 1802 1803 bb.3.exit: 1804 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 1805 1806... 1807--- 1808name: illegal_vaddva_s16 1809alignment: 2 1810tracksRegLiveness: true 1811registers: [] 1812liveins: 1813 - { reg: '$r0', virtual-reg: '' } 1814 - { reg: '$r1', virtual-reg: '' } 1815 - { reg: '$r2', virtual-reg: '' } 1816 - { reg: '$r3', virtual-reg: '' } 1817frameInfo: 1818 stackSize: 8 1819 offsetAdjustment: 0 1820 maxAlignment: 8 1821 stackProtector: '' 1822 maxCallFrameSize: 0 1823 cvBytesOfCalleeSavedRegisters: 0 1824 localFrameSize: 0 1825 savePoint: '' 1826 restorePoint: '' 1827fixedStack: 1828 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 1829 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 1830 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1831stack: 1832 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1833 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1834 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1835 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1836 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 1837 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1838callSites: [] 1839constants: [] 1840machineFunctionInfo: {} 1841body: | 1842 ; CHECK-LABEL: name: illegal_vaddva_s16 1843 ; CHECK: bb.0.entry: 1844 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1845 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 1846 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1847 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1848 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1849 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 1850 ; CHECK: tCBZ $r1, %bb.4 1851 ; CHECK: bb.1.vector.ph: 1852 ; CHECK: successors: %bb.2(0x80000000) 1853 ; CHECK: liveins: $r0, $r1, $r2, $r3 1854 ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 1855 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1856 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1857 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1858 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1859 ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 1860 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1861 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1862 ; CHECK: dead $lr = t2DLS renamable $r2 1863 ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1864 ; CHECK: bb.2.vector.body: 1865 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1866 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 1867 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg 1868 ; CHECK: MVE_VPST 8, implicit $vpr 1869 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) 1870 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 1871 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1872 ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 1873 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1874 ; CHECK: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 1875 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 1876 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1877 ; CHECK: bb.3.exit: 1878 ; CHECK: liveins: $r3 1879 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1880 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1881 ; CHECK: bb.4: 1882 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1883 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1884 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1885 bb.0.entry: 1886 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1887 liveins: $r0, $r1, $r2, $r3, $r4, $lr 1888 1889 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1890 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1891 frame-setup CFI_INSTRUCTION offset $lr, -4 1892 frame-setup CFI_INSTRUCTION offset $r4, -8 1893 tCBZ $r1, %bb.4 1894 1895 bb.1.vector.ph: 1896 successors: %bb.2(0x80000000) 1897 liveins: $r0, $r1, $r2, $r3 1898 1899 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 1900 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1901 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1902 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1903 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1904 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 1905 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1906 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1907 $lr = t2DoLoopStart renamable $r2 1908 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1909 1910 bb.2.vector.body: 1911 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1912 liveins: $q0, $r0, $r1, $r3, $r4 1913 1914 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg 1915 MVE_VPST 8, implicit $vpr 1916 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) 1917 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 1918 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1919 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 1920 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1921 renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 1922 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 1923 renamable $lr = t2LoopDec killed renamable $lr, 1 1924 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1925 tB %bb.3, 14 /* CC::al */, $noreg 1926 1927 bb.3.exit: 1928 liveins: $r3 1929 1930 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1931 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1932 1933 bb.4: 1934 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1935 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1936 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1937 1938... 1939--- 1940name: illegal_vaddv_u16 1941alignment: 2 1942tracksRegLiveness: true 1943registers: [] 1944liveins: 1945 - { reg: '$r0', virtual-reg: '' } 1946 - { reg: '$r1', virtual-reg: '' } 1947 - { reg: '$r2', virtual-reg: '' } 1948frameInfo: 1949 stackSize: 8 1950 offsetAdjustment: 0 1951 maxAlignment: 8 1952 stackProtector: '' 1953 maxCallFrameSize: 0 1954 cvBytesOfCalleeSavedRegisters: 0 1955 localFrameSize: 0 1956 savePoint: '' 1957 restorePoint: '' 1958fixedStack: 1959 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 1960 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 1961 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1962stack: 1963 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1964 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1965 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1966 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1967 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 1968 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1969callSites: [] 1970constants: [] 1971machineFunctionInfo: {} 1972body: | 1973 ; CHECK-LABEL: name: illegal_vaddv_u16 1974 ; CHECK: bb.0.entry: 1975 ; CHECK: successors: %bb.1(0x80000000) 1976 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 1977 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1978 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1979 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1980 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 1981 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1982 ; CHECK: t2IT 0, 8, implicit-def $itstate 1983 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 1984 ; CHECK: bb.1.vector.ph: 1985 ; CHECK: successors: %bb.2(0x80000000) 1986 ; CHECK: liveins: $r0, $r1, $r2 1987 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1988 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1989 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1990 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1991 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1992 ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 1993 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 1994 ; CHECK: dead $lr = t2DLS renamable $r12 1995 ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1996 ; CHECK: bb.2.vector.body: 1997 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1998 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 1999 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 2000 ; CHECK: MVE_VPST 8, implicit $vpr 2001 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) 2002 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2003 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2004 ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 2005 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2006 ; CHECK: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 2007 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 2008 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2009 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2010 ; CHECK: bb.3.exit: 2011 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2012 bb.0.entry: 2013 successors: %bb.1(0x80000000) 2014 liveins: $r0, $r1, $r2, $r4, $lr 2015 2016 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2017 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2018 frame-setup CFI_INSTRUCTION offset $lr, -4 2019 frame-setup CFI_INSTRUCTION offset $r4, -8 2020 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2021 t2IT 0, 8, implicit-def $itstate 2022 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2023 2024 bb.1.vector.ph: 2025 successors: %bb.2(0x80000000) 2026 liveins: $r0, $r1, $r2, $r4, $lr 2027 2028 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 2029 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 2030 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 2031 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2032 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 2033 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2034 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 2035 $lr = t2DoLoopStart renamable $r12 2036 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2037 2038 bb.2.vector.body: 2039 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2040 liveins: $q0, $r0, $r1, $r2, $r4 2041 2042 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 2043 MVE_VPST 8, implicit $vpr 2044 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) 2045 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2046 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2047 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 2048 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2049 renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 2050 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 2051 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2052 renamable $lr = t2LoopDec killed renamable $lr, 1 2053 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2054 tB %bb.3, 14 /* CC::al */, $noreg 2055 2056 bb.3.exit: 2057 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2058 2059... 2060--- 2061name: illegal_vaddva_u16 2062alignment: 2 2063tracksRegLiveness: true 2064registers: [] 2065liveins: 2066 - { reg: '$r0', virtual-reg: '' } 2067 - { reg: '$r1', virtual-reg: '' } 2068 - { reg: '$r2', virtual-reg: '' } 2069 - { reg: '$r3', virtual-reg: '' } 2070frameInfo: 2071 stackSize: 8 2072 offsetAdjustment: 0 2073 maxAlignment: 8 2074 stackProtector: '' 2075 maxCallFrameSize: 0 2076 cvBytesOfCalleeSavedRegisters: 0 2077 localFrameSize: 0 2078 savePoint: '' 2079 restorePoint: '' 2080fixedStack: 2081 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2082 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2083 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2084stack: 2085 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2086 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2087 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2088 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2089 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2090 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2091callSites: [] 2092constants: [] 2093machineFunctionInfo: {} 2094body: | 2095 ; CHECK-LABEL: name: illegal_vaddva_u16 2096 ; CHECK: bb.0.entry: 2097 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2098 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2099 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2100 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2101 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2102 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 2103 ; CHECK: tCBZ $r1, %bb.4 2104 ; CHECK: bb.1.vector.ph: 2105 ; CHECK: successors: %bb.2(0x80000000) 2106 ; CHECK: liveins: $r0, $r1, $r2, $r3 2107 ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2108 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 2109 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 2110 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2111 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2112 ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2113 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 2114 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2115 ; CHECK: dead $lr = t2DLS renamable $r2 2116 ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2117 ; CHECK: bb.2.vector.body: 2118 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2119 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 2120 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg 2121 ; CHECK: MVE_VPST 8, implicit $vpr 2122 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) 2123 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2124 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2125 ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 2126 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2127 ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2128 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 2129 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2130 ; CHECK: bb.3.exit: 2131 ; CHECK: liveins: $r3 2132 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2133 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2134 ; CHECK: bb.4: 2135 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2136 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2137 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2138 bb.0.entry: 2139 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2140 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2141 2142 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2143 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2144 frame-setup CFI_INSTRUCTION offset $lr, -4 2145 frame-setup CFI_INSTRUCTION offset $r4, -8 2146 tCBZ $r1, %bb.4 2147 2148 bb.1.vector.ph: 2149 successors: %bb.2(0x80000000) 2150 liveins: $r0, $r1, $r2, $r3 2151 2152 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2153 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 2154 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 2155 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2156 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2157 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2158 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 2159 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2160 $lr = t2DoLoopStart renamable $r2 2161 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2162 2163 bb.2.vector.body: 2164 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2165 liveins: $q0, $r0, $r1, $r3, $r4 2166 2167 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg 2168 MVE_VPST 8, implicit $vpr 2169 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) 2170 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2171 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2172 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg 2173 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2174 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2175 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 2176 renamable $lr = t2LoopDec killed renamable $lr, 1 2177 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2178 tB %bb.3, 14 /* CC::al */, $noreg 2179 2180 bb.3.exit: 2181 liveins: $r3 2182 2183 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2184 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2185 2186 bb.4: 2187 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2188 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2189 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2190 2191... 2192--- 2193name: illegal_vaddv_s8 2194alignment: 2 2195tracksRegLiveness: true 2196registers: [] 2197liveins: 2198 - { reg: '$r0', virtual-reg: '' } 2199 - { reg: '$r1', virtual-reg: '' } 2200 - { reg: '$r2', virtual-reg: '' } 2201frameInfo: 2202 stackSize: 8 2203 offsetAdjustment: 0 2204 maxAlignment: 8 2205 stackProtector: '' 2206 maxCallFrameSize: 0 2207 cvBytesOfCalleeSavedRegisters: 0 2208 localFrameSize: 0 2209 savePoint: '' 2210 restorePoint: '' 2211fixedStack: 2212 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 2213 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2214 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2215stack: 2216 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2217 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2218 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2219 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2220 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2221 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2222callSites: [] 2223constants: [] 2224machineFunctionInfo: {} 2225body: | 2226 ; CHECK-LABEL: name: illegal_vaddv_s8 2227 ; CHECK: bb.0.entry: 2228 ; CHECK: successors: %bb.1(0x80000000) 2229 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 2230 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2231 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2232 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2233 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 2234 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2235 ; CHECK: t2IT 0, 8, implicit-def $itstate 2236 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2237 ; CHECK: bb.1.vector.ph: 2238 ; CHECK: successors: %bb.2(0x80000000) 2239 ; CHECK: liveins: $r0, $r1, $r2 2240 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2241 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2242 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2243 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2244 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2245 ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2246 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 2247 ; CHECK: dead $lr = t2DLS renamable $r12 2248 ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2249 ; CHECK: bb.2.vector.body: 2250 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2251 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 2252 ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg 2253 ; CHECK: MVE_VPST 8, implicit $vpr 2254 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2255 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2256 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2257 ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2258 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2259 ; CHECK: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2260 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2261 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2262 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2263 ; CHECK: bb.3.exit: 2264 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2265 bb.0.entry: 2266 successors: %bb.1(0x80000000) 2267 liveins: $r0, $r1, $r2, $r4, $lr 2268 2269 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2270 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2271 frame-setup CFI_INSTRUCTION offset $lr, -4 2272 frame-setup CFI_INSTRUCTION offset $r4, -8 2273 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2274 t2IT 0, 8, implicit-def $itstate 2275 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2276 2277 bb.1.vector.ph: 2278 successors: %bb.2(0x80000000) 2279 liveins: $r0, $r1, $r2, $r4, $lr 2280 2281 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2282 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2283 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2284 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2285 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2286 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2287 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 2288 $lr = t2DoLoopStart renamable $r12 2289 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2290 2291 bb.2.vector.body: 2292 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2293 liveins: $q0, $r0, $r1, $r2, $r4 2294 2295 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg 2296 MVE_VPST 8, implicit $vpr 2297 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2298 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2299 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2300 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2301 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2302 renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2303 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2304 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2305 renamable $lr = t2LoopDec killed renamable $lr, 1 2306 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2307 tB %bb.3, 14 /* CC::al */, $noreg 2308 2309 bb.3.exit: 2310 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2311 2312... 2313--- 2314name: illegal_vaddva_s8 2315alignment: 2 2316tracksRegLiveness: true 2317registers: [] 2318liveins: 2319 - { reg: '$r0', virtual-reg: '' } 2320 - { reg: '$r1', virtual-reg: '' } 2321 - { reg: '$r2', virtual-reg: '' } 2322 - { reg: '$r3', virtual-reg: '' } 2323frameInfo: 2324 stackSize: 8 2325 offsetAdjustment: 0 2326 maxAlignment: 8 2327 stackProtector: '' 2328 maxCallFrameSize: 0 2329 cvBytesOfCalleeSavedRegisters: 0 2330 localFrameSize: 0 2331 savePoint: '' 2332 restorePoint: '' 2333fixedStack: 2334 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2335 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2336 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2337stack: 2338 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2339 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2340 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2341 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2342 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2343 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2344callSites: [] 2345constants: [] 2346machineFunctionInfo: {} 2347body: | 2348 ; CHECK-LABEL: name: illegal_vaddva_s8 2349 ; CHECK: bb.0.entry: 2350 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2351 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2352 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2353 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2354 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2355 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 2356 ; CHECK: tCBZ $r1, %bb.4 2357 ; CHECK: bb.1.vector.ph: 2358 ; CHECK: successors: %bb.2(0x80000000) 2359 ; CHECK: liveins: $r0, $r1, $r2, $r3 2360 ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2361 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2362 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2363 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2364 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2365 ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2366 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2367 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2368 ; CHECK: dead $lr = t2DLS renamable $r2 2369 ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2370 ; CHECK: bb.2.vector.body: 2371 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2372 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 2373 ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg 2374 ; CHECK: MVE_VPST 8, implicit $vpr 2375 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2376 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2377 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2378 ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2379 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2380 ; CHECK: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2381 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2382 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2383 ; CHECK: bb.3.exit: 2384 ; CHECK: liveins: $r3 2385 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2386 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2387 ; CHECK: bb.4: 2388 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2389 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2390 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2391 bb.0.entry: 2392 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2393 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2394 2395 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2396 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2397 frame-setup CFI_INSTRUCTION offset $lr, -4 2398 frame-setup CFI_INSTRUCTION offset $r4, -8 2399 tCBZ $r1, %bb.4 2400 2401 bb.1.vector.ph: 2402 successors: %bb.2(0x80000000) 2403 liveins: $r0, $r1, $r2, $r3 2404 2405 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2406 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2407 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2408 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2409 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2410 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2411 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2412 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2413 $lr = t2DoLoopStart renamable $r2 2414 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2415 2416 bb.2.vector.body: 2417 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2418 liveins: $q0, $r0, $r1, $r3, $r4 2419 2420 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg 2421 MVE_VPST 8, implicit $vpr 2422 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2423 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2424 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2425 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2426 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2427 renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2428 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2429 renamable $lr = t2LoopDec killed renamable $lr, 1 2430 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2431 tB %bb.3, 14 /* CC::al */, $noreg 2432 2433 bb.3.exit: 2434 liveins: $r3 2435 2436 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2437 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2438 2439 bb.4: 2440 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2441 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2442 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2443 2444... 2445--- 2446name: illegal_vaddv_u8 2447alignment: 2 2448tracksRegLiveness: true 2449registers: [] 2450liveins: 2451 - { reg: '$r0', virtual-reg: '' } 2452 - { reg: '$r1', virtual-reg: '' } 2453 - { reg: '$r2', virtual-reg: '' } 2454frameInfo: 2455 stackSize: 8 2456 offsetAdjustment: 0 2457 maxAlignment: 8 2458 stackProtector: '' 2459 maxCallFrameSize: 0 2460 cvBytesOfCalleeSavedRegisters: 0 2461 localFrameSize: 0 2462 savePoint: '' 2463 restorePoint: '' 2464fixedStack: 2465 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 2466 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2467 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2468stack: 2469 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2470 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2471 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2472 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2473 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2474 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2475callSites: [] 2476constants: [] 2477machineFunctionInfo: {} 2478body: | 2479 ; CHECK-LABEL: name: illegal_vaddv_u8 2480 ; CHECK: bb.0.entry: 2481 ; CHECK: successors: %bb.1(0x80000000) 2482 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 2483 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2484 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2485 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2486 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 2487 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2488 ; CHECK: t2IT 0, 8, implicit-def $itstate 2489 ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2490 ; CHECK: bb.1.vector.ph: 2491 ; CHECK: successors: %bb.2(0x80000000) 2492 ; CHECK: liveins: $r0, $r1, $r2 2493 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2494 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2495 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2496 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2497 ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2498 ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2499 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 2500 ; CHECK: dead $lr = t2DLS renamable $r12 2501 ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2502 ; CHECK: bb.2.vector.body: 2503 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2504 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 2505 ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg 2506 ; CHECK: MVE_VPST 8, implicit $vpr 2507 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2508 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2509 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2510 ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2511 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2512 ; CHECK: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2513 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2514 ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2515 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2516 ; CHECK: bb.3.exit: 2517 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2518 bb.0.entry: 2519 successors: %bb.1(0x80000000) 2520 liveins: $r0, $r1, $r2, $r4, $lr 2521 2522 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2523 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2524 frame-setup CFI_INSTRUCTION offset $lr, -4 2525 frame-setup CFI_INSTRUCTION offset $r4, -8 2526 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2527 t2IT 0, 8, implicit-def $itstate 2528 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2529 2530 bb.1.vector.ph: 2531 successors: %bb.2(0x80000000) 2532 liveins: $r0, $r1, $r2, $r4, $lr 2533 2534 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2535 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2536 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2537 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2538 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2539 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2540 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) 2541 $lr = t2DoLoopStart renamable $r12 2542 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2543 2544 bb.2.vector.body: 2545 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2546 liveins: $q0, $r0, $r1, $r2, $r4 2547 2548 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg 2549 MVE_VPST 8, implicit $vpr 2550 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2551 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2552 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2553 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2554 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2555 renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2556 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2557 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) 2558 renamable $lr = t2LoopDec killed renamable $lr, 1 2559 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2560 tB %bb.3, 14 /* CC::al */, $noreg 2561 2562 bb.3.exit: 2563 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2564 2565... 2566--- 2567name: illegal_vaddva_u8 2568alignment: 2 2569tracksRegLiveness: true 2570registers: [] 2571liveins: 2572 - { reg: '$r0', virtual-reg: '' } 2573 - { reg: '$r1', virtual-reg: '' } 2574 - { reg: '$r2', virtual-reg: '' } 2575 - { reg: '$r3', virtual-reg: '' } 2576frameInfo: 2577 stackSize: 8 2578 offsetAdjustment: 0 2579 maxAlignment: 8 2580 stackProtector: '' 2581 maxCallFrameSize: 0 2582 cvBytesOfCalleeSavedRegisters: 0 2583 localFrameSize: 0 2584 savePoint: '' 2585 restorePoint: '' 2586fixedStack: 2587 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2588 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2589 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2590stack: 2591 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2592 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2593 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2594 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2595 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2596 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2597callSites: [] 2598constants: [] 2599machineFunctionInfo: {} 2600body: | 2601 ; CHECK-LABEL: name: illegal_vaddva_u8 2602 ; CHECK: bb.0.entry: 2603 ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2604 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2605 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2606 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2607 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2608 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 2609 ; CHECK: tCBZ $r1, %bb.4 2610 ; CHECK: bb.1.vector.ph: 2611 ; CHECK: successors: %bb.2(0x80000000) 2612 ; CHECK: liveins: $r0, $r1, $r2, $r3 2613 ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2614 ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2615 ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2616 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2617 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2618 ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2619 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2620 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2621 ; CHECK: dead $lr = t2DLS renamable $r2 2622 ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2623 ; CHECK: bb.2.vector.body: 2624 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2625 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 2626 ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg 2627 ; CHECK: MVE_VPST 8, implicit $vpr 2628 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2629 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2630 ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2631 ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2632 ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2633 ; CHECK: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2634 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2635 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2636 ; CHECK: bb.3.exit: 2637 ; CHECK: liveins: $r3 2638 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2639 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2640 ; CHECK: bb.4: 2641 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2642 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2643 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2644 bb.0.entry: 2645 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2646 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2647 2648 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2649 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2650 frame-setup CFI_INSTRUCTION offset $lr, -4 2651 frame-setup CFI_INSTRUCTION offset $r4, -8 2652 tCBZ $r1, %bb.4 2653 2654 bb.1.vector.ph: 2655 successors: %bb.2(0x80000000) 2656 liveins: $r0, $r1, $r2, $r3 2657 2658 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2659 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2660 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2661 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2662 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2663 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) 2664 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2665 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2666 $lr = t2DoLoopStart renamable $r2 2667 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2668 2669 bb.2.vector.body: 2670 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2671 liveins: $q0, $r0, $r1, $r3, $r4 2672 2673 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg 2674 MVE_VPST 8, implicit $vpr 2675 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) 2676 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 2677 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2678 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg 2679 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2680 renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2681 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2682 renamable $lr = t2LoopDec killed renamable $lr, 1 2683 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2684 tB %bb.3, 14 /* CC::al */, $noreg 2685 2686 bb.3.exit: 2687 liveins: $r3 2688 2689 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2690 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2691 2692 bb.4: 2693 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2694 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2695 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2696 2697... 2698--- 2699name: regalloc_legality_vaddva_u32 2700alignment: 2 2701tracksRegLiveness: true 2702registers: [] 2703liveins: 2704 - { reg: '$r0', virtual-reg: '' } 2705 - { reg: '$r1', virtual-reg: '' } 2706 - { reg: '$r2', virtual-reg: '' } 2707frameInfo: 2708 stackSize: 8 2709 offsetAdjustment: 0 2710 maxAlignment: 4 2711 stackProtector: '' 2712 maxCallFrameSize: 0 2713 cvBytesOfCalleeSavedRegisters: 0 2714 localFrameSize: 0 2715 savePoint: '' 2716 restorePoint: '' 2717fixedStack: [] 2718stack: 2719 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2720 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2721 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2722 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2723 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 2724 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2725callSites: [] 2726constants: [] 2727machineFunctionInfo: {} 2728body: | 2729 ; CHECK-LABEL: name: regalloc_legality_vaddva_u32 2730 ; CHECK: bb.0.entry: 2731 ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) 2732 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 2733 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2734 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2735 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2736 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 2737 ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2738 ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2739 ; CHECK: bb.1.while.body.preheader: 2740 ; CHECK: successors: %bb.2(0x80000000) 2741 ; CHECK: liveins: $r0, $r1, $r2 2742 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2743 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 2744 ; CHECK: bb.2.while.body: 2745 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2746 ; CHECK: liveins: $lr, $r0, $r1, $r12 2747 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.tmp3, align 2) 2748 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.tmp1, align 2) 2749 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 2750 ; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg 2751 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 2752 ; CHECK: bb.3.while.end: 2753 ; CHECK: liveins: $r12 2754 ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2755 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2756 ; CHECK: bb.4: 2757 ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2758 ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2759 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2760 bb.0.entry: 2761 successors: %bb.1(0x50000000), %bb.4(0x30000000) 2762 liveins: $r0, $r1, $r2, $r7, $lr 2763 2764 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2765 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2766 frame-setup CFI_INSTRUCTION offset $lr, -4 2767 frame-setup CFI_INSTRUCTION offset $r7, -8 2768 tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 2769 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg 2770 t2IT 10, 8, implicit-def $itstate 2771 renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate 2772 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2773 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2774 2775 bb.1.while.body.preheader: 2776 successors: %bb.2(0x80000000) 2777 liveins: $r0, $r1, $r2, $r3 2778 2779 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg 2780 renamable $r12 = t2ADDri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 2781 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2782 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 2783 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2784 $lr = t2DoLoopStart renamable $lr 2785 2786 bb.2.while.body: 2787 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2788 liveins: $lr, $r0, $r1, $r2, $r12 2789 2790 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 2791 MVE_VPST 4, implicit $vpr 2792 renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.tmp3, align 2) 2793 renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.tmp1, align 2) 2794 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 2795 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2796 renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg 2797 renamable $lr = t2LoopDec killed renamable $lr, 1 2798 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 2799 tB %bb.3, 14 /* CC::al */, $noreg 2800 2801 bb.3.while.end: 2802 liveins: $r12 2803 2804 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2805 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2806 2807 bb.4: 2808 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2809 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2810 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2811 2812... 2813--- 2814name: regalloc_legality_vaddv_u16 2815alignment: 2 2816tracksRegLiveness: true 2817registers: [] 2818liveins: 2819 - { reg: '$r0', virtual-reg: '' } 2820 - { reg: '$r1', virtual-reg: '' } 2821 - { reg: '$r2', virtual-reg: '' } 2822frameInfo: 2823 stackSize: 8 2824 offsetAdjustment: 0 2825 maxAlignment: 4 2826 stackProtector: '' 2827 maxCallFrameSize: 0 2828 cvBytesOfCalleeSavedRegisters: 0 2829 localFrameSize: 0 2830 savePoint: '' 2831 restorePoint: '' 2832fixedStack: [] 2833stack: 2834 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2835 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2836 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2837 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2838 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 2839 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2840callSites: [] 2841constants: [] 2842machineFunctionInfo: {} 2843body: | 2844 ; CHECK-LABEL: name: regalloc_legality_vaddv_u16 2845 ; CHECK: bb.0.entry: 2846 ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) 2847 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 2848 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2849 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2850 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2851 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 2852 ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2853 ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2854 ; CHECK: bb.1.while.body.preheader: 2855 ; CHECK: successors: %bb.2(0x80000000) 2856 ; CHECK: liveins: $r0, $r1, $r2 2857 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2858 ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 2859 ; CHECK: bb.2.while.body: 2860 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2861 ; CHECK: liveins: $lr, $r0, $r1, $r3 2862 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.tmp3, align 2) 2863 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.tmp1, align 2) 2864 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 2865 ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg 2866 ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg 2867 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 2868 ; CHECK: bb.3.while.end: 2869 ; CHECK: liveins: $r3 2870 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2871 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2872 ; CHECK: bb.4: 2873 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2874 ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2875 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2876 bb.0.entry: 2877 successors: %bb.1(0x50000000), %bb.4(0x30000000) 2878 liveins: $r0, $r1, $r2, $r7, $lr 2879 2880 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2881 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2882 frame-setup CFI_INSTRUCTION offset $lr, -4 2883 frame-setup CFI_INSTRUCTION offset $r7, -8 2884 tCMPi8 renamable $r2, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 2885 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg 2886 t2IT 10, 8, implicit-def $itstate 2887 renamable $r3 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate 2888 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2889 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2890 2891 bb.1.while.body.preheader: 2892 successors: %bb.2(0x80000000) 2893 liveins: $r0, $r1, $r2, $r3 2894 2895 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg 2896 renamable $r12 = t2ADDri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2897 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2898 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2899 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2900 $lr = t2DoLoopStart renamable $lr 2901 2902 bb.2.while.body: 2903 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2904 liveins: $lr, $r0, $r1, $r2, $r3 2905 2906 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 2907 MVE_VPST 4, implicit $vpr 2908 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) 2909 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) 2910 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 2911 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 2912 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg 2913 renamable $lr = t2LoopDec killed renamable $lr, 1 2914 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg 2915 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 2916 tB %bb.3, 14 /* CC::al */, $noreg 2917 2918 bb.3.while.end: 2919 liveins: $r3 2920 2921 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2922 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2923 2924 bb.4: 2925 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2926 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2927 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2928 2929... 2930--- 2931name: regalloc_illegality_vaddva_s32 2932alignment: 2 2933tracksRegLiveness: true 2934registers: [] 2935liveins: 2936 - { reg: '$r0', virtual-reg: '' } 2937 - { reg: '$r1', virtual-reg: '' } 2938 - { reg: '$r3', virtual-reg: '' } 2939frameInfo: 2940 stackSize: 8 2941 offsetAdjustment: 0 2942 maxAlignment: 4 2943 stackProtector: '' 2944 maxCallFrameSize: 0 2945 cvBytesOfCalleeSavedRegisters: 0 2946 localFrameSize: 0 2947 savePoint: '' 2948 restorePoint: '' 2949fixedStack: [] 2950stack: 2951 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2952 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2953 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2954 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2955 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 2956 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2957callSites: [] 2958constants: [] 2959machineFunctionInfo: {} 2960body: | 2961 ; CHECK-LABEL: name: regalloc_illegality_vaddva_s32 2962 ; CHECK: bb.0.entry: 2963 ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) 2964 ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 2965 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2966 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2967 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 2968 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 2969 ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 2970 ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 2971 ; CHECK: t2IT 10, 8, implicit-def $itstate 2972 ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 2973 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2974 ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2975 ; CHECK: bb.1.while.body.preheader: 2976 ; CHECK: successors: %bb.2(0x80000000) 2977 ; CHECK: liveins: $r0, $r1, $r2, $r3 2978 ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 2979 ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2980 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2981 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2982 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2983 ; CHECK: $lr = t2DLS killed renamable $lr 2984 ; CHECK: bb.2.while.body: 2985 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2986 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 2987 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg 2988 ; CHECK: MVE_VPST 4, implicit $vpr 2989 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) 2990 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) 2991 ; CHECK: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 2992 ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 2993 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 2994 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 2995 ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 2996 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 2997 ; CHECK: bb.3.while.end: 2998 ; CHECK: liveins: $r2 2999 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3000 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3001 ; CHECK: bb.4: 3002 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3003 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3004 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3005 bb.0.entry: 3006 successors: %bb.1(0x50000000), %bb.4(0x30000000) 3007 liveins: $r0, $r1, $r3, $r7, $lr 3008 3009 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3010 frame-setup CFI_INSTRUCTION def_cfa_offset 8 3011 frame-setup CFI_INSTRUCTION offset $lr, -4 3012 frame-setup CFI_INSTRUCTION offset $r7, -8 3013 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3014 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3015 t2IT 10, 8, implicit-def $itstate 3016 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3017 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3018 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3019 3020 bb.1.while.body.preheader: 3021 successors: %bb.2(0x80000000) 3022 liveins: $r0, $r1, $r2, $r3 3023 3024 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3025 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3026 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3027 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3028 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3029 $lr = t2DoLoopStart renamable $lr 3030 3031 bb.2.while.body: 3032 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3033 liveins: $lr, $r0, $r1, $r2, $r3 3034 3035 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg 3036 MVE_VPST 4, implicit $vpr 3037 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) 3038 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) 3039 renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 3040 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 3041 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 3042 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3043 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 3044 renamable $lr = t2LoopDec killed renamable $lr, 1 3045 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 3046 tB %bb.3, 14 /* CC::al */, $noreg 3047 3048 bb.3.while.end: 3049 liveins: $r2 3050 3051 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3052 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3053 3054 bb.4: 3055 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3056 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3057 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3058 3059... 3060--- 3061name: illegal_vmull_non_zero 3062alignment: 2 3063tracksRegLiveness: true 3064registers: [] 3065liveins: 3066 - { reg: '$r0', virtual-reg: '' } 3067 - { reg: '$r1', virtual-reg: '' } 3068 - { reg: '$r3', virtual-reg: '' } 3069frameInfo: 3070 stackSize: 8 3071 offsetAdjustment: 0 3072 maxAlignment: 4 3073fixedStack: [] 3074stack: 3075 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 3076 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 3077 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3078 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 3079 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 3080 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3081callSites: [] 3082constants: [] 3083machineFunctionInfo: {} 3084body: | 3085 ; CHECK-LABEL: name: illegal_vmull_non_zero 3086 ; CHECK: bb.0.entry: 3087 ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) 3088 ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 3089 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3090 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 3091 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 3092 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 3093 ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3094 ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3095 ; CHECK: t2IT 10, 8, implicit-def $itstate 3096 ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3097 ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3098 ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3099 ; CHECK: bb.1.while.body.preheader: 3100 ; CHECK: successors: %bb.2(0x80000000) 3101 ; CHECK: liveins: $r0, $r1, $r2, $r3 3102 ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3103 ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3104 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3105 ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3106 ; CHECK: dead $lr = t2DLS renamable $r2 3107 ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3108 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3109 ; CHECK: bb.2.while.body: 3110 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3111 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 3112 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg 3113 ; CHECK: MVE_VPST 4, implicit $vpr 3114 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) 3115 ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) 3116 ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 3117 ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 3118 ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 3119 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3120 ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 3121 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 3122 ; CHECK: bb.3.while.end: 3123 ; CHECK: liveins: $r2 3124 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3125 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3126 ; CHECK: bb.4: 3127 ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3128 ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3129 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3130 bb.0.entry: 3131 successors: %bb.1(0x50000000), %bb.4(0x30000000) 3132 liveins: $r0, $r1, $r3, $r7, $lr 3133 3134 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3135 frame-setup CFI_INSTRUCTION def_cfa_offset 8 3136 frame-setup CFI_INSTRUCTION offset $lr, -4 3137 frame-setup CFI_INSTRUCTION offset $r7, -8 3138 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3139 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3140 t2IT 10, 8, implicit-def $itstate 3141 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3142 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3143 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3144 3145 bb.1.while.body.preheader: 3146 successors: %bb.2(0x80000000) 3147 liveins: $r0, $r1, $r2, $r3 3148 3149 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3150 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3151 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3152 renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3153 $lr = t2DoLoopStart renamable $r2 3154 $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3155 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3156 3157 bb.2.while.body: 3158 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3159 liveins: $r0, $r1, $r2, $r3, $r12 3160 3161 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg 3162 MVE_VPST 4, implicit $vpr 3163 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) 3164 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) 3165 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 3166 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 3167 renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 3168 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3169 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg 3170 renamable $lr = t2LoopDec killed renamable $lr, 1 3171 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 3172 tB %bb.3, 14 /* CC::al */, $noreg 3173 3174 bb.3.while.end: 3175 liveins: $r2 3176 3177 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3178 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3179 3180 bb.4: 3181 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3182 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3183 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3184 3185... 3186